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| The Western Design Center, Inc. Updated June 14, 2004 W65C816S Data Sheet www..com W65C816S Microprocessor DATA SHEET WDC (c) The Western Design Center, Inc., 2004. All rights reserved The Western Design Center, Inc. W65C816S Data Sheet WDC reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Information contained herein is provided gratuitously and without liability, to any user. Reasonable efforts have been made to verify accuracy of the information but no guarantee whatsoever is given as to the accuracy or as to its applicability to particular uses. In every instance, it www..combe the responsibility of the user to determine the suitability of the products for each application. must WDC products are not authorized for use as critical components in life support devices or systems. Nothing contained herein shall be construed as a recommendation to use any product in violation of existing patents or other rights of third parties. The sale of any WDC product is subject to all WDC Terms and Conditions of Sales and Sales Policies, copies of which are available upon request. Copyright (C) 1981-2004 by The Western Design Center, Inc. All rights reserved, including the right of reproduction in whole or in part in any form. The Western Design Center W65C816S 2 The Western Design Center, Inc. W65C816S Data Sheet TABLE OF CONTENTS 1 2 INTRODUCTION ........................................................................................................................... 7 W65C816S FUNCTIONAL DESCRIPTION................................................................................. 8 Instruction Register (IR).......................................................................................................... 8 Timing Control Unit (TCU)...................................................................................................... 8 Arithmetic and Logic Unit (ALU)............................................................................................. 8 Internal Registers (Refer to Programming Model Table 2-2) ................................................... 8 Accumulator (A)....................................................................................................................... 8 Data Bank Register (DBR)....................................................................................................... 9 Direct (D) ................................................................................................................................. 9 Index (X and Y) ........................................................................................................................ 9 Processor Status Register (P).................................................................................................... 9 Program Bank Register (PBR)................................................................................................. 9 Program Counter (PC)........................................................................................................... 10 Stack Pointer (S) .................................................................................................................... 10 Abort (ABORTB)................................................................................................................... 16 Address Bus (A0-A15)............................................................................................................ 16 Bus Enable (BE)..................................................................................................................... 16 Data/Bank Address Bus (D0-D7)............................................................................................ 16 Emulation Status (E).............................................................................................................. 17 Interrupt Request (IRQB)...................................................................................................... 17 Memory Lock (MLB)............................................................................................................. 17 Memory/Index Select Status (MX) ......................................................................................... 17 Non-Maskable Interrupt (NMIB)........................................................................................... 18 Phase 2 In (PHI2)................................................................................................................... 18 Read/Write (RWB)................................................................................................................. 18 Ready (RDY).......................................................................................................................... 18 Reset (RESB).......................................................................................................................... 19 Valid Data Address (VDA) and Valid Program Address (VPA)............................................. 19 VDD and VSS......................................................................................................................... 19 Vector Pull (VPB)................................................................................................................... 19 2.1 2.2 2.3 2.4 www..com 2.5 2.6 2.7 2.8 2.9 2.10 2.11 2.12 3 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 PIN FUNCTION DESCRIPTION ............................................................................................... 13 4 4.1 4.2 4.3 4.4 4.5 ADDRESSING MODES ............................................................................................................... 20 Reset and Interrupt Vectors ................................................................................................... 20 Stack ...................................................................................................................................... 20 Direct ..................................................................................................................................... 20 Program Address Space ......................................................................................................... 20 Data Address Space................................................................................................................ 20 Absolute-a .........................................................................................................................................................................................21 Absolute Indexed Indirect-(a,x) .....................................................................................................................................................21 Absolute Indexed with X-a,x .........................................................................................................................................................21 Absolute Indexed with Y-a,y .........................................................................................................................................................21 Absolute Indirect-(a)........................................................................................................................................................................22 Absolute Long Indexed With X-al,x.............................................................................................................................................22 Absolute Long-al..............................................................................................................................................................................22 Accumulator-A .................................................................................................................................................................................22 The Western Design Center W65C816S 3 The Western Design Center, Inc. W65C816S Data Sheet Block Move-xyc ...............................................................................................................................................................................22 Direct Indexed Indirect-(d,x)..........................................................................................................................................................23 Direct Indexed with X-d,x ..............................................................................................................................................................23 Direct Indexed with Y-d,y ..............................................................................................................................................................23 Direct Indirect Indexed-(d),y..........................................................................................................................................................24 Direct Indirect Long Indexed-[d],y ...............................................................................................................................................24 Direct Indirect Long-[d]..................................................................................................................................................................24 Direct Indirect-(d) ............................................................................................................................................................................25 Direct-d ..............................................................................................................................................................................................25 Immediate-# ......................................................................................................................................................................................25 Implied-i ............................................................................................................................................................................................25 www..com Program Counter Relative Long-rl................................................................................................................................................25 Program Counter Relative-r ...........................................................................................................................................................26 Stack-s ................................................................................................................................................................................................26 Stack Relative-d,s.............................................................................................................................................................................26 Stack Relative Indirect Indexed-(d,s),y ........................................................................................................................................26 5 5.1 5.2 TIMING, AC AND DC CHARACTERISTICS............................................................................ 28 Absolute Maximum Ratings ................................................................................................... 28 DC Characteristics TA = -40C to +85C.............................................................................. 29 6 7 7.1 7.2 7.3 OPERATION TABLES................................................................................................................. 32 RECOMMENDED W65C816S ASSEMBLER SYNTAX STANDARDS................................... 52 Directives ............................................................................................................................... 52 Comments .............................................................................................................................. 52 The Source Line ..................................................................................................................... 52 7.3.1 7.3.2 7.3.3 7.3.4 The Label Field.................................................................................................................................................................52 The Operation Code Field ..............................................................................................................................................52 The Operand Field ...........................................................................................................................................................53 Comment Field .................................................................................................................................................................55 8 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9 8.10 8.11 8.12 8.13 8.14 8.15 8.16 8.17 8.18 8.19 8.20 Caveats........................................................................................................................................... 56 Stack Addressing.................................................................................................................... 57 Direct Addressing................................................................................................................... 57 Absolute Indexed Addressing ................................................................................................. 57 ABORTB Input...................................................................................................................... 57 VDA and VPA Valid Memory Address Output Signals .......................................................... 57 DB/BA operation when RDY is Pulled Low............................................................................ 58 MX Output............................................................................................................................. 58 All OpCodes Function in All Modes of Operation.................................................................. 58 Indirect Jumps ....................................................................................................................... 58 Switching Modes .................................................................................................................... 58 How Interrupts Affect the Program Bank and the Data Bank Registers ................................ 58 Binary Mode .......................................................................................................................... 59 WAI Instruction..................................................................................................................... 59 The STP Instruction............................................................................................................... 59 COP Signatures...................................................................................................................... 59 WDM OpCode Use................................................................................................................. 59 RDY Pulled During Write ...................................................................................................... 59 MVN and MVP Affects on the Data Bank Register................................................................ 59 Interrupt Priorities................................................................................................................. 60 Transfers from 8-Bit to 16-Bit, or 16-Bit to 8-Bit Registers .................................................... 60 The Western Design Center W65C816S 4 The Western Design Center, Inc. W65C816S Data Sheet 8.21 8.22 8.23 Stack Transfers ...................................................................................................................... 60 BRK Instruction..................................................................................................................... 60 Accumulator switching from 8 bit to 16 bit ............................................................................ 60 9 9.1 HARD CORE MODEL ................................................................................................................. 61 W65C816 Core Information................................................................................................... 61 10 10.1 SOFT CORE RTL MODEL...................................................................................................... 61 W65C816 Synthesizable RTL-Code in Verilog HDL.............................................................. 61 11 www..com ORDERING INFORMATION ................................................................................................. 62 The Western Design Center W65C816S 5 The Western Design Center, Inc. W65C816S Data Sheet Table of Tables Table 2-1 W65C816S Microprocessor Programming Model...................................................................... 12 Table 3-1 Pin Function Table ......................................................................................................................... 16 Table 4-1 Addressing Mode Summary .......................................................................................................... 27 Table 5-1 Absolute Maximum Ratings .......................................................................................................... 28 Table 5-2 DC Characteristics ......................................................................................................................... 29 Table 5-3 IDD vs. VDD ................................................................................................................................... 29 Table 5- 4 F Max vs. VDD............................................................................................................................... 29 Table 5-4 W65C816S AC Characteristics ..................................................................................................... 30 www..com Table 6-1 W65C816S Instruction Set-Alphabetical Sequence .................................................................... 32 Table 6-2 Emulation Mode Vector Locations (8-bit Mode )......................................................................... 34 Table 6-3 Native Mode Vector Locations (16-bit Mode) ............................................................................. 34 Table 6-4 OpCode Matrix ............................................................................................................................... 35 Table 6-5 Operation, Operation Codes, and Status Register (continued on following 4 pages)............... 36 Table 6-6 Addressing Mode Symbol Table ................................................................................................... 41 Table 6-7 Instruction Operation (continued on following 6 pages)............................................................ 42 Table 6-8 Abbreviations .................................................................................................................................. 50 Table 7-1 Alternate Mnemonics ..................................................................................................................... 53 Table 7-2 Address Mode Formats .................................................................................................................. 54 Table 7-3 Byte Selection Operator................................................................................................................. 55 Table 8-1 Caveats ............................................................................................................................................ 56 Table of Figures Figure 2-1 Figure 3-1 Figure 3-2 Figure 3-3 Figure 5-1 Figure 6-1 W65C816S Internal Architecture Simplified Block Diagram.................................................. 11 W65C816S 44 Pin PLCC Pinout ................................................................................................. 13 W65C816S 40 Pin PDIP Pinout ................................................................................................... 14 W65C816S 44 PIN QFP Pinout ................................................................................................... 15 General Timing Diagram............................................................................................................. 31 Bank Address Latching Circuit .................................................................................................... 51 The Western Design Center W65C816S 6 The Western Design Center, Inc. W65C816S Data Sheet 1 INTRODUCTION The W65C816S is a low power c sensitive 16-bit microprocessor. The variable length instruction set and manually ost optimized core size makes the W65C816S an excellent choice for low power System-on-Chip (SoC) designs. The Verilog RTL model is available for ASIC design flows. WDC, a Fabless Semiconductor Company, provides packaged chips for evaluation or volume production. To aid in system development, WDC provides a Development System that includes a W65C816DB Developer Board, an In-Circuit Emulator (ICE) and the W65cSDS Software Development System, see www.westerndesigncenter.com for more information. The WDC W65C816S is a fully static CMOS 16-bit microprocessor featuring software compatibility* with the 8-bit NMOS and CMOS 6500-series predecessors. The W65C816S extends addressing to a full 16 megabytes. These devices offer the www..com many advantages of CMOS technology, including increased noise immunity, higher reliability, and greatly reduced power requirements. A software switch determines whether the processor is in the 8-bit "emulation" mode, or in the native mode, thus allowing existing systems to use the expanded features. As shown in the W65C816S Processor Programming Model, Figure 2-2, the Accumulator, ALU, X and Y Index registers, and Stack Pointer register have all been extended to 16 bits. A new 16-bit Direct Page register augments the Direct Page addressing mode (formerly Zero Page addressing). Separate Program Bank and Data Bank registers provide 24-bit memory addressing with segmented or linear addressing. Four new signals provide the system designer with many options. The ABORTB input can interrupt the currently executing instruction without modifying internal register, thus allowing virtual memory system design. Valid Data Address (VDA) and Valid Program Address (VPA) outputs facilitate dual cache memory by indicating whether a data segment or program segment is accessed. Modifying a vector is made easy by monitoring the Vector Pull (VPB) output. KEY FEATURES OF THE W65C816S * Advanced fully static CMOS design for low power * Low power consumption (300uA@1MHz) consumption and increased noise immunity * Separate program and data bank registers allow * Wide operating voltage range, 1.8+/- 5%, 2.5+/- 5%, program segmentation or full 16 MByte linear 3.0+/- 5%, 3.3+/ - 10%, 5.0+/- 5% specified for use addressing with advanced low voltage peripherals * New Direct Register and stack relative addressing * Emulation mode allows complete hardware and provides capability for re-entrant, re-cursive and resoftware compatibility with 6502 designs locatable programming * 24-bit address bus provides access to 16 MBytes of * 24 addressing modes - 13 original 6502 modes with 92 memory space instructions using 256 OpCodes * Full 16-bit ALU, Accumulator, Stack Pointer and * Wait-for-Interrupt (WAI) and Stop-the-Clock (STP) Index Registers instructions further reduce power consumption, decrease interrupt latency and allows synchronization * Valid Data Address (VDA) and Valid Program with external events Address (VPA) output for dual cache and cycle steal DMA imple mentation * Co-Processor (COP) instruction with associated vector supports co-processor configurations, i.e., floating point * Vector Pull (VPB) output indicates when interrupt processors vectors are being addressed * Block move ability * Abort (ABORTB) input and associated vector supports processor repairs of bus error conditions *Except for the BBRx, BBSx, RMBx, and SMBx bit manipulation instructions which do not exist for the W65C816S The Western Design Center W65C816S 7 The Western Design Center, Inc. W65C816S Data Sheet 2 W65C816S FUNCTIONAL DESCRIPTION The W65C816S provides the design engineer with upward software compatibility from 8-bit W65C02 in applications to 16-bit system application. In Emulation mode, the W65C816S offers many advantages, including full software compatibility with 6502 coding. Internal organization of the W65C816S can be divided into two parts: 1) The Register Section and 2) The Control Section. Instructions obtained from program memory are executed by implementing a series of data transfers within the Register Section. Signals that cause data transfers to be executed are generated within the Control Section. The W65C816S has a 16-bit internal bus architecture with an 8-bit external data bus and 24-bit external www..com address bus. 2.1 Instruction Register (IR) An Operation Code enters the processor on the Data Bus, and is latched into the Instruction Register during the OpCode fetch cycle. This OpCode is then decoded, along with timing and interrupt signals, to generate various Instruction Register control signals for use during instruction operations. 2.2 Timing Control Unit (TCU) The Timing Control Unit keeps track of each instruction cycle as it is executed. The TCU is set to zero each time an instruction fetch is executed, and is advanced at the beginning of each cycle for as many cycles as is required to complete the instruction. Each data transfer between registers depends upon decoding the contents of both the Instruction Register and the Timing Control Unit. 2.3 Arithmetic and Logic Unit (ALU) All arithmetic and logic operations take place within the 16-bit ALU. In addition to data operations, the ALU also calculates the effective address for relative and indexed addressing modes. The result of a data operation is stored in either memory or an internal register. Carry, Negative, Overflow and Zero flags may be updated following the ALU data operation. 2.4 2.5 Internal Registers (Refer to Programming Model Table 2-2) Accumulator (A) The Accumulator (A) is a general purpose register which contains one of the operands and the result of most arithmetic and logical operations. In the Native mode (E=0), when the Accumulator Select Bit (M) equals zero, the Accumulator is established as 16 bits wide (A, B=C). When the Accumulator Select Bit (M) equals one, the Accumulator is 8 bits wide (A). In this case, the upper 8 bits (B) may be used for temporary storage in conjunction with the Exchange Accumulator (XBA) instruction. The Western Design Center W65C816S 8 The Western Design Center, Inc. W65C816S Data Sheet 2.6 Data Bank Register (DBR) During modes of operation, the 8-bit Data Bank Register (DBR) holds the bank address for memory transfers. The 24-bit address is composed of the 16-bit instruction effective address and the 8-bit Data Bank address. The register value is multiplexed with the data value and is present on the Data/Address lines during the first half of a data transfer memory cycle for the W65C816S. The Data Bank Register is initialized to zero during Reset. 2.7 www..com Direct (D) The 16-bit Direct Register (D) provides an address offset for all instructions using direct addressing. The effective Direct Address is formed by adding the 8-bit instruction Direct Address field to the Direct Register. The Direct Register is initialized to zero during Reset. The bank address for Direct Addressing is always zero 2.8 Index (X and Y) There are two general purpose registers that are commonly referred to as Index Registers (X and Y) and are frequently used as an index value for calculation of the effective address. When executing an instruction with indexed addressing, the microprocessor fetches the OpCode and the base address, and then modifies the address by adding an Index Register contents to the address prior to performing the desired operation. Pre-indexing or post-indexing of indirect addresses may be selected. In the Native mode (E=0), both Index Registers are 16 bits wide where the Index Select Bit (X) of the Processor Status (P) register equals zero. If the Index Select Bit (X) equals one, both registers will be 8 bits wide, and the high byte is forced to zero. 2.9 Processor Status Register (P) The 8-bit Processor Status Register (P) contains status flags and mode select bits. The Carry (C), Negative (N), Overflow (V), and Zero (Z) status flags serve to report the status of most ALU operations. These status flags are tested by use of Conditional Branch instructions. The Decimal (D), IRQ Disable (I), Memory/Accumulator (M), and Index (X) bits are used as mode select flags. These flags are set by the program to change microprocessor operations. The Emulation (E) select and the Break (B) flags are accessible only through the Processor Status Register. The Emulation mode select flag is selected by the Exchange Carry and Emulation Bits (XCE) instruction. Table 8-1, W65C816S Compatibility Information, illustrates the features of the Native (E=0) and Emulation (E=1) modes. The M and X flags are always equal to one in Emulation mode. When an interrupt occurs during Emulation mode, the Break flag is written to stack memory as bit 4 of the Processor Status Register. 2.10 Program Bank Register (PBR) The 8-bit Program Bank Register (PBR) holds the bank address for all instruction fetches. The 24-bit address consists of the 16-bit instruction effective address and the 8 Program Bank address. The register value is -bit multiplexed with the data bus and presented on the Data bus lines during the first half of a program memory cycle. The Program Bank Register is initialized to zero during Reset. The PHK instruction pushes the PBR register onto the Stack. The Western Design Center W65C816S 9 The Western Design Center, Inc. W65C816S Data Sheet 2.11 Program Counter (PC) The 16-bit Program Counter (PC) Register provides the addresses which are used to step the microprocessor through sequential 8-bit program instruction fields. The PC is incremented for each 8-bit instruction field that is fetched from program memory. 2.12 www..com Stack Pointer (S) The Stack Pointer (S) is a 16-bit register which is used to indicate the next available location in the stack memory area. It serves as the effective address in stack addressing modes as well as subroutine and interrupt processing. The Stack Pointer provides simple implementation of nested subroutines and multiple -level interrupts. During Emulation mode, the S High-order byte (SH) is always equal to one. The bank address for all stack operations is Bank zero. The Western Design Center W65C816S 10 The Western Design Center, Inc. W65C816S Data Sheet VDD INDEX X (16 BITS) INDEX Y (16 BITS) STACK POINTER (S) (16 BITS) ADDRESS BUFFER (LOW) INTERUPT LOGIC INTERNAL SPECIAL BUS (16 BITS) AO-A7 www..com VSS ABORTB IRQB NMIB RESB ALU (16 BITS) INTERNAL ADDRESS BUS (16 BITS) ADDRESS BUFFER (HIGH) INSTRUCTION DECODE SUM OF MINTERMS REGISTER TRANSFER LOGIC ACCUMULATOR (C) (16 BITS) (A) (8 BITS) (B) (8 BITS) INSTRUCTION DECODE MINTERMS A8-A15 INTERNAL DATA BUS (16 BITS) TRANSFER SWITCHES TIMING CONT. RDY CLOCK GENERATOR PHI2 PROG. COUNTER (PC) (16 BITS) DIRECT (D) (16 BITS) PROG. BANK (PBR) (8 BITS) DATABANK(DBR) (8BITS) DATA BUS/BANK ADDRESS BUFFER RWB VPA VDA MLB VPB E MX DO-D7 (816) DATA LATCH/ PREDECODE PROCESSOR STATUS (P) (8 BITS) PREDECODE INSTRUCTION REGISTER (8 BITS) SYSTEM CONT. BE Figure 2-1W65C816S Internal Architecture Simplified Block Diagram The Western Design Center W65C816S 11 The Western Design Center, Inc. W65C816S Data Sheet Table 2-1 W65C816S Microprocessor Programming Model 8 BITS Data Bank Register (DBR) Data Bank Register (DBR) 00 www..com 8 BITS X Register (XH) Y Register (YH) Stack Register (SH) Accumulator (B) 8 BITS X Register (XL) Y Register (YL) Stack Register (SL) (C) Accumulator (A) Counter (PCL) Direct Register (DL) Program Bank Register (PBR) 00 Shaded blocks = 6502 registers Program (PCH) Direct Register (DH) 1 N V M B X BRK command: 1=BRK 0=IRQ D I Z E C Carry 1=true Zero 1=result zero IRQ disable 1=disable Decimal mode 1=true Index Register Select 1=8-bit, 0=16-bit Memory Select 1=8-bit, 0=16-bit Overflow 1=true Emulation 1=6502 Emulation Mode Negative 1=negative 0=Native Mode The Western Design Center W65C816S 12 The Western Design Center, Inc. W65C816S Data Sheet 3 PIN FUNCTION DESCRIPTION ABORTB RESB IRQB MLB VDA RDY VPB VSS MX 6 5 4 3 2 1 44 43 42 41 BE 40 39 38 37 36 www..com PHI2 NMIB VPA VDD A0 A1 NC A2 A3 A4 A5 A6 7 8 9 10 11 12 13 14 15 16 17 18 A7 19 A8 20 A9 21 A10 22 A11 23 VSS 24 VSS 25 A12 26 A13 27 A14 28 A15 NC RWB VDD D0 D1 D2 D3 D4 D5 D6 D7 W65C816S 35 34 33 32 31 30 29 Figure 3-1 W65C816S 44 Pin PLCC Pinout The Western Design Center W65C816S 13 The Western Design Center, Inc. W65C816S Data Sheet www..com VPB RDY ABORT IRQB MLB NMIB VPA VDD A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 W65C816S RESB VDA MX PHI2 BE E RWB D0 D1 D2 D3 D4 D5 D6 D7 A15 A14 A13 A12 VSS Figure 3-2 W65C816S 40 Pin PDIP Pinout The Western Design Center W65C816S 14 The Western Design Center, Inc. W65C816S Data Sheet ABORTB RESB IRQB MLB VDA RDY PHI2 35 VPB VSS MX www..com 44 NMIB VPA VDD A0 A1 NC A2 A3 A4 A5 A6 1 2 3 4 5 6 7 8 9 10 11 12 A7 43 42 41 40 39 38 37 36 34 33 32 31 30 29 E RWB VDD D0 D1 D2 D3 D4 D5 D6 D7 W65C816S BE 28 27 26 25 24 23 22 13 A8 14 A9 15 A10 16 A11 17 VSS 18 VSS 19 A12 20 A13 21 A14 Figure 3-3 W65C816S 44 PIN QFP Pinout The Western Design Center W65C816S A15 15 The Western Design Center, Inc. W65C816S Data Sheet Table 3-1 Pin Function Table Pin A0-A15 ABORTB BE PHI2 D0-D7 E IRQB MLB MX NC NMIB RDY RESB RWB VDA VPB VPA VDD VSS Description Address Bus Abort Input Bus Enable Phase 2 In Clock Data Bus/Bank Address Bus Emulation OR Native Mode Select Interrupt Request Memory Lock Memory and Index Register Mode Select www..com No Connect Non-Maskable Interrupt Ready Reset Read/Write Valid Data Address Vector Pull Valid Program Address Positive Power Supply Internal Logic Ground 3.1 Abort (ABORTB) The Abort (ABORTB) negative pulse active input is used to abort instructions (usually due to an Address Bus condition). A negative transition will inhibit modification of any internal register during the current instruction. Upon completion of this instruction, an interrupt sequence is initiated. The location of the aborted OpCode is stored as the return address in stack memory. The Abort vector address is 00FFF8,9 (Emulation mode) or 00FFE8,9 (Native mode). Note that ABORTB is a pulse-sensitive signal; i.e., an abort will occur whenever there is a negative pulse (or level) on the ABORTB pin during a PHI2 clock. 3.2 Address Bus (A0-A15) The sixteen Address Bus (A0-A15) output lines along with the bank address (multiplexed on the first half cycle of the Data Bus (D0-D7) pins) form the 24-bit Address Bus for memory and I/O exchange on the Data Bus. When using the W65C816S, the address lines may be set to the high impedance state by the Bus Enable (BE) signal. 3.3 Bus Enable (BE) The Bus Enable (BE) input signal allows external control of the Address and Data Buffers, as well as the RWB signal. With Bus Enable high, the RWB and Address Buffers are active. The Data/Address Buffers are active during the first half of every cycle and the second half of a write cycle. When BE is low, these buffers are disabled. Bus Enable is an asynchronous signal. 3.4 Data/Bank Address Bus (D0-D7) The Western Design Center W65C816S 16 The Western Design Center, Inc. W65C816S Data Sheet The Data/Bank Address Bus (D0-D7) pins provide both the Bank Address and Data. The bank address is present during the first half of a memory cycle, and the data value is read or written during the second half of the memory cycle. Two memory cycles are required to transfer 16-bit values. These lines may be set to the high impedance state by the Bus Enable (BE) signal. 3.5 Emulation Status (E) The Emulation Status (E) output reflects the state of the Emulation (E) mode flag in the Processor Status (P) Register. This signal may be thought of as an OpCode extension and used for memory and system management. www..com 3.6 Interrupt Request (IRQB) The Interrupt Request (IRQB) negative level active input signal is used to request that an interrupt sequence be initiated. When the IRQB Disable (I) flag is cleared, a low input logic level initiates an interrupt sequence after the current instruction is completed. The Wait-for-Interrupt (WAI) instruction may be executed to ensure the interrupt will be recognized immediately. The Interrupt Request vector address is 00FFFE,F (Emulation mode) or 00FFEE,F (Native mode). Since IRQB is a level-sensitive input, an interrupt will occur if the interrupt source was not cleared since the last interrupt. Also, no interrupt will occur if the interrupt source is cleared prior to interrupt recognition. The IRQB signal going low causes 4 bytes of information to be pushed onto the stack before jumping to the interrupt handler. The first byte is PBR followed by PCH, PCL and P (Processor Status Register). These register values are used by the RTI instruction to return the processor to its original state prior to handling the IRQ interrupt (see Table 6-1) 3.7 Memory Lock (MLB) The Memory Lock (MLB) active low output may be used to ens ure the integrity of Read-Modify-Write instructions in a multiprocessor system. Memory Lock indicates the need to defer arbitration of the next bus cycle. Memory Lock is low during the last three or five cycles of ASL, DEC, INC, LSR, ROL, ROR, TRB, and TSB memory referencing instructions, depending on the state of the M flag. 3.8 Memory/Index Select Status (MX) The Memory/Index Select Status (MX) multiplexed output reflects the state of the Accumulator (M) and Index (X) elect flags (bits 5 and 4 of the Processor Status (P) Register. Flag M is valid during PHI2 negative transition and Flag X is valid during PHI2 positive transition. These bits may be thought of as OpCode extensions and may be used for memory and system management. The Western Design Center W65C816S 17 The Western Design Center, Inc. W65C816S Data Sheet 3.9 Non-Maskable Interrupt (NMIB) A negative transition on the Non-Maskable Interrupt (NMIB) input initiates an interrupt sequence. A high-to-low transition initiates an interrupt sequence after the current instruction is completed. The Wait for Interrupt (WAI) instruction may be executed to ensure that the interrupt will be recognized immediately. The Non-Maskable Interrupt vector address is 00FFFA,B (Emulation mode) or 00FFEA,B (Native mode). Since NMIB is an edge-sensitive input, an interrupt will occur if there is a negative transition while servicing a previous interrupt. No interrupt will occur if NMIB remains low after the negative transition was processed. The NMIB signal going low causes 4 bytes of information to be pushed onto the stack before jumping to the interrupt handler. The first www..com the stack is the PBR followed by the PCH, PCL and P, these register values are used by the RTI byte on instruction to return the processor to its original state prior to the NMI interrupt. 3.10 Phase 2 In (PHI2) Phase 2 In (PHI2) is the system clock input to the microprocessor. PHI2 can be held in either state to preserve the contents of internal registers and reduce power as a Standby mode. 3.11 Read/Write (RWB) The Read/Write (RWB) output signal is used to control whether the microprocessor is "Reading" or "Writing" to memory. When the RWB is in the high state, the microprocessor is reading data from memory or I/O. When RBW is low the Data Bus contains valid data from the microprocessor which is to written to the addressed memory location. The RWB signal is set to the high impedance state when Bus Enable (BE) is low. 3.12 Ready (RDY) The Ready (RDY) is a bi-directional signal. When it is an output it indicates that a Wait for Interrupt (WAI) instruction has been executed halting operation of the microprocessor. A low input logic level will halt the microprocessor in its current state. Returning RDY to the active high state releases the microprocessor to continue processing following the next PHI2 negative transition. The RDY signal is internally pulled low following the execution of a Wait for Interrupt (WAI) instruction, and then returned to the high state when a RESB, ABORTB, NMIB, or IRQB external interrupt is active. This feature may be used to reduce interrupt latency by executing the WAI instruction and waiting for an interrupt to begin processing. If the IRQB Disable flag has been set, the next instruction will be executed when the IRQB occurs. The processor will not stop after a WAI instruction if RDY has been forced to a high state. The Stop (STP) instruction has no effect on RDY. The RDY pin has an active pull-up and when outputting a low level, the pull-up is turned off to reduce power. The RDY pin can be wired ORed. The Western Design Center W65C816S 18 The Western Design Center, Inc. W65C816S Data Sheet 3.13 Reset (RESB) The Reset (RESB) active low input is used to initialize the microprocessor and start program execution. The Reset input buffer has hysteresis such that a simple R-C timing circuit may be used with the internal pull-up device. The RESB signal must be held low for at least two clock cycles after VDD reaches operating voltage. Ready (RDY) has no effect while RESB is being held low. The stack pointer must be initialized by the user's software. During the Reset conditioning period the following processor initialization takes place: D=0000 DBR=00 www..com PBR=00 Registers SH=01, SL=* XH=00, XL=* YH=00, YL=* A=* P Register N * V * M 1 X 1 D 0 I 1 Z * C/E */1 *=not initialized Signals E=1 VDA=0 MX=1 VPB=1 RWB=1 VPA=0 When Reset is brought high, an interrupt sequence is initiated * STP and WAI instructions are cleared * RWB remains in the high state during the stack address cycles. * The Reset vector address is 00FFFC,D.(see Table 6-1 for Vectors) * PC is loaded with the contents of 00FFFC,D 3.14 Valid Data Address (VDA) and Valid Program Address (VPA) The Valid Data Address (VDA) and Valid Program Address (VDA) output signals indicate valid memory addresses when high and are used for memory or I/O address qualification. VDA 0 0 1 1 VPA 0 1 0 1 Internal Operation Address and Data Bus available. The Address Bus may be invalid. Valid program address-may be used for program cache control. Valid data address-may be used for data cache control. OpCode fetch-may be used for program cache control and single step control 3.15 VDD and VSS VDD is the positive supply voltage and VSS is system logic ground. 3.16 Vector Pull (VPB) The Vector Pull (VPB) active low output indicates that a vector location is being addressed during an interrupt sequence. VPB is low during the last two interrupt sequence cycles, during which time the processor loads the PC with the interrupt handler vector location. The VPB signal may be used to select and prioritize interrupts from several sources by modifying the vector addresses. The Western Design Center W65C816S 19 The Western Design Center, Inc. W65C816S Data Sheet 4 ADDRESSING MODES The W65C816S is capable of directly addressing 16 MBytes of memory. This address space has special significance within certain addressing modes, as follows: 4.1 Reset and Interrupt Vectors The Reset and Interrupt Vectors use the majority of the fixed addresses between 00FFE0 and 00FFFF. 4.2 www..com Stack The Stack may be use memory from 000000 to 00FFFF. The effective address of Stack and Stack Relative addressing modes will be always be within this range. 4.3 Direct The Direct addressing modes are usually used to store memory registers and pointers. The effective address generated by Direct, Direct,X and Direct,Y addressing modes is always in Bank 0 (000000-00FFFF). 4.4 Program Address Space The Program Bank register is not affected by the Relative, Relative Long, Absolute, Absolute Indirect, and Absolute Indexed Indirect addressing modes or by incrementing the Program Counter from FFFF. The only instructions that affect the Program Bank register are: RTI, RTL, JML, JSL, and JMP Absolute Long. Program code may exceed 64K bytes although code segments may not span bank boundaries. 4.5 Data Address Space The Data Address space is contiguous throughout the 16 MByte address space. Words, arrays, records, or any data structures may span 64 KByte bank boundaries with no compromise in code efficiency. The following addressing modes generate 24-bit effective addresses: * * * * * * * * * * * Absolute a Absolute a,x Absolute a,y Absolute Long al Absolute Long Indexed al,x Direct Indexed Indirect (d,x) Direct Indirect (d) Direct Indirect Indexed (d),y Direct Indirect Long [d] Direct Indirect Long Indexed [d],y Stack Relative Indirect Indexed (d,x),y The following addressing mode descriptions provide additional detail as to how effective addresses are calculated. Twenty-four addressing modes are available for the W65C816S. The Western Design Center W65C816S 20 The Western Design Center, Inc. W65C816S Data Sheet Absolute -a With Absolute (a) addressing the second and third bytes of the instruction form the low-order 16 bits of the effective address. The Data Bank Register contains the high-order 8 bits of the operand address. Instruction: Operand Absolute Indexed Indirect-(a,x) OpCode DBR addrl addrh addrh addrl With Absolute Indexed Indirect ((a,x)) addressing the second and third bytes of the instruction are added to the X Index www..com Register to form a 16-bit pointer in Bank 0. The contents of this pointer are loaded in the Program Counter for the JMP instruction. The Program Bank Register is not changed. Instruction: OpCode addrl addrh PBR then: PC = (address) Abs olute Indexed with X-a,x addrh addrl X Reg address With Absolute Indexed with X (a,x) addressing the second and third bytes of the instruction are added to the X Index Register to form the low-order 16-bits of the effective address. The Data Bank Register contains the high-order 8 bits of the effective address. Instruction: OpCode DBR + Operand Address: Absolute Indexed with Y-a,y effective address addrl addrh addrh addrl X Reg With Absolute Indexed with Y (a,y) addressing the second and third bytes of the instruction are added to the Y Index Register to form the low-order 16-bits of the effective address. The Data Bank Register contains the high-order 8 bits of the effective address. Instruction: OpCode DBR + Operand Address: effective address addrl addrh addrh addrl Y Reg The Western Design Center W65C816S 21 The Western Design Center, Inc. W65C816S Data Sheet Absolute Indirect-(a) With Absolute Indirect ((a)) addressing the second and third bytes of the instruction form an address to a pointer in Bank 0. The Program Counter is loaded with the first and second bytes at this pointer. With the Jump Long (JML) instruction, the Program Bank Register is loaded with the third byte of the pointer. Instruction: Indirect Absolute Long Indexed With X-al,x www..com OpCode addrl 00 addrh addrh addrl With Absolute Long Indexed with X (al,x) addressing the second, third and fourth bytes of the instruction form a 24-bit base address. The effective address is the sum of this 24-bit address and the X Index Register. Instruction: OpCode baddr + Operand Address: Absolute Long-al effective address addrl addrh addrh addrl X Reg baddr With Absolute Long (al) addressing the second, third and fourth byte of the instruction form the 24-bit effective address. Instruction: Operand Address: Accumulator-A OpCode baddr addrl addrh addrh addrl baddr With Accumulator (A) addressing the operand is the Accumulator. Block Move-xyc Block Move (xyc) addressing is used by the Block Move instructions. The second byte of the instruction contains the high-order 8 bits of the destination address and the Y Index Register contains the low-order 16 bits of the destination address. The third byte of the instruction contains the high-order 8 bits of the source address and the X Index Register contains the low-order bits of the source address. The C Accumulator contains one less than the number of bytes to move. The second byte of the block move instructions is also loaded into the Data Bank Register. Instruction: Source Address: Dest. Address; OpCode dstbnk srcbnk DBR srcbnk X Reg Y Reg dstbnk Y DBR Increment X and Y (MVN) or decrement X and Y (MVP) and decrement C (if greater than zero), then PC=PC+3. The Western Design Center W65C816S 22 The Western Design Center, Inc. W65C816S Data Sheet Direct Indexed Indirect-(d,x) Direct Indexed Indirect ((d,x)) addressing is often referred to as Indirect X addressing. The second byte of the instruction is added to the sum of the Direct Register and the X Index Register. The result points to the X low-order 16 bits of the effective address. The Data Bank Register contains the high-order 8 bits of the effective address. Instruction: www..com OpCode + + 00 offset Direct Register offset direct address X Reg (address) then: + DBR effective address Operand Address: Direct Indexed with X-d,x With Direct Indexed with X (d,x) addressing the second byte of the instruction is added to the sum of the Direct Register and the X Index Register to form the 16-bit effective address. The operand is always in Bank 0. Instruction: OpCode + + Operand Address: Direct Indexed with Y-d,y 00 offset Direct Register offset direct address X Reg effective address With Direct Indexed with Y (d,y) addressing the second byte of the instruction is added to the sum of the Direct Register and the Y Index Register to form the 16-bit effective address. The operand is always in Bank 0. Instruction: OpCode + + Operand Address: 00 offset Direct Register offset direct address Y Reg effective address The Western Design Center W65C816S 23 The Western Design Center, Inc. W65C816S Data Sheet Direct Indirect Indexed-(d),y Direct Indirect Indexed ((d),y) addressing is often referred to as Indirect Y addressing. The second byte of the instruction is added to the Direct Register (D). The 16-bit content of this memory location is then combined with the Data Bank register to form a 24-bit base address. The Y Index Register is added to the base address to form the effective address. Instruction: www..com OpCode + 00 offset Direct Register offset (direct address) base address then: + + DBR Y Reg effective address Operand Address: Direct Indirect Long Indexed-[d],y With Direct Indirect Long Indexed ([d],y) addressing the 24-bit base address is pointed to by the sum of the second byte of the instruction and the Direct Register. The effective address is this 24-bit base address plus the Y Index Register. Instruction: OpCode + 00 then Operand Address: Direct Indirect Long-[d] + effective address base address Y Reg offset Direct Register offset direct address With Direct Indirect Long ([d]) addressing the second byte of the instruction is added to the Direct Register to form a pointer to the 24-bit effective address. Instruction: then: 00 Operand Address: OpCode + direct address offset Direct Register offset (direct address) The Western Design Center W65C816S 24 The Western Design Center, Inc. W65C816S Data Sheet Direct Indirect-(d) With Direct Indirect ((d)) addressing the second byte of the instruction is added to the Direct Register to form a pointer to the low-order 16 bits of the effective address. The Data Bank Register contains the high-order 8 bits of the effective address. Instruction: OpCode + www..com offset Direct Register offset (direct address) effective address 00 then: + DBR Operand Address: Direct-d With Direct (d) addressing the second byte of the instruction is added to the Direct Register (D) to form the effective address. An additional cycle is required when the Direct Register is not page aligned (DL not equal 0). The Bank register is always 0. Instruction: OpCode + Operand Address: 00 offset Direct Register offset effective address Immediate-# With Immediate (#) addressing the operand is the second byte (second and third bytes when in the 16-bit mode) of the instruction. Implied-i Implied (i) addressing uses a single byte instruction. The operand is implicitly defined by the instruction. Program Counter Relative Long-rl The Program Counter Relative Long (rl) addressing mode is used with only with the unconditional Branch Long instruction (BRL) and the Push Effective Relative instruction (PER). The second and third bytes of the instruction are added to the Program Counter, which has been updated to point to the OpCode of the next instruction. With the branch instruction, the Program Counter is loaded with the result. With the Push Effective Relative instruction, the result is stored on the stack. The offset is a signed 16-bit quantity in the range from -32768 to 32767. The Program Bank Register is not affected. The Western Design Center W65C816S 25 The Western Design Center, Inc. W65C816S Data Sheet Program Counter Relative -r The Program Counter Relative (r) addressing is referred to as Relative Addressing and is used o with the nly Branch instructions. If the condition being tested is met, the second byte of the instruction is added to the Program Counter, which has been updated to point to the OpCode of the next instruction. The offset is a signed 8 -bit quantity in the range from -128 to 127. The Program Bank Register is not affected. Stack-s Stack www..com (s) addressing refers to all instructions that push or pull data from the stack, such as Push, Pull, Jump to Subroutine, Return from Subroutine, Interrupts, and Return from Interrupt. The bank address is always 0. Interrupt Vectors are always fetched from Bank 0. Stack Relative -d,s With Stack Relative (d,s) addressing the low-order 16 bits of the effective address is formed from the sum of the second byte of the instruction and the stack pointer. The high-order 8 bits of the effective address are always zero. The relative offset is an unsigned 8-bit quantity in the range of 0 to 255. Instruction: then: Operand Address: OpCode + 00 offset Stack Pointer offset effective address Stack Relative Indirect Indexed-(d,s),y With Stack Relative Indirect Indexed ((d,s),y) addressing the second byte of the instruction is added to the Stack Pointer to form a pointer to the low-order 16-bit base address in Bank 0. The Data Bank Register contains the high-order 8 bits of the base address. The effective address is the sum of the 24-bit base address and the Y Index Register. Instruction: OpCode offset Stack Pointer offset 00 then + Operand Address: effective address + DBR base address Y Reg S + offset The Western Design Center W65C816S 26 The Western Design Center, Inc. W65C816S Data Sheet Table 4-1 Addressing Mode Summary Address Mode Instruction Times in Memory Cycle Original 8-bit NMOS 6502 4 (5) 5 4 (1,5) 4 (1) 2 3 (5) 6 5 (1) 4 (5) 4 2 2 2 (1,2) 3-7 New W65C816S www..com Absolute Absolute Indexed Indirect (Jump) Absolute Indirect (Jump) Absolute Long Absolute Long, X Absolute, X Absolute, Y Accumulator Block Move (xyc) Direct Direct Indexed Indirect (d,x) Direct Indirect Direct Indirect Indexed (d),y Direct Indirect Indexed Long [d],y Direct Indirect Long Direct, X Direct, Y Immediate Implied Relative Relative Long Stack Stack Relative Stack Relative Indirect Indexed 4 (3,5) 6 5 5 (3) 5 (3) 4 (1,3,5) 4 (1,3) 2 7 3 (3,4,5) 6 (3,4) 5 (3,4) 5 (1,3,4) 6 (3,4) 6 (3,4) 4 (3,4,5) 4 (3,4) 2 (3) 2 2 (2) 3 (2) 3-8 4 (3) 7 (3) Memory Utilization in Number of Program Sequence Bytes Original 8-bit New NMOS W65C816S 6502 3 3 3 3 3 4 4 3 3 1 2 2 2 2 2 2 1 2 1-3 3 3 1 3 2 2 2 2 2 2 2 2 2 (3) 1 2 3 1-4 2 2 Notes (these are indicated in parentheses): 1. Page boundary, add 1 cycle if page boundary is crossed when forming address. 2. Branch taken, add 1 cycle if branch is taken. 3. M = 0 or X = 0, 16 bit operation, add 1 cycle, add 1 byte for immediate. 4. Direct register low (DL) not equal zero, add 1 cycle. 5. Read-Modify-Write, add 2 cycles for M = 1, add 3 cycles for M = 0. The Western Design Center W65C816S 27 The Western Design Center, Inc. W65C816S Data Sheet 5 5.1 TIMING, AC AND DC CHARACTERISTICS Absolute Maximum Ratings Table 5-1 Absolute Maximum Ratings Rating Supply Voltage Input Voltage Storage Temperature Symbol VDD VIN TS Value -0.3 to +7.0V -0.3 to VDD +0.3V -55C to +150C www..com This device contains input protection against damage due to high static voltages or electric fields; however, precautions should be taken to avoid application of voltages higher than the maximum rating. Note: Exceeding these ratings may result in permanent damage. Functional operation under the not implied. conditions is The Western Design Center W65C816S 28 The Western Design Center, Inc. W65C816S Data Sheet 5.2 DC Characteristics TA = -40C to +85C Table 5-2 DC Characteristics Symbol VDO Input High Voltage ABORTB, BE, Data, IRQB, RDY, NMIB, PHI2, RESB Input Low Voltage Vil ABORTB, BE, Data, IRQB, RDY, NMIB, PHI2, RESB www..com Pullup-Current RDY Input Ipup (VIN=VDDx0.8) Vih Iin Input Leakage Current (Vin=0.4 to 2.4) PHI2, Address, Data, RWB, (Off state, BE=0), All other inputs Output High Voltage (Vol=VDD-0.4V) Min 4.25 5.0 +/ - 5% Max 5.25 VDD+0.3 3.3 +/ - 10% Min Max 3.0 3.6 VDDx0.8 VDD+0.3 Min 2.85 3.0 +/ - 5% Max 3.15 VDD+0.3 2.5 +/ - 5% Min Max 2.375 2.625 VDDx0.8 VDD+0.3 Min 1.71 1.8 +/ - 5% Max 1.89 VDD+0.3 Units V V VDDx0.8 VDDx0.8 VDDx0.8 VSS-0.3 5 -0.2 700 1.6 - VDDx0.2 20 0.2 2.0 1.0 VSS-0.3 5 -0.2 300 1.6 - VDDx0.2 20 0.2 1.5 0.6 1 VSS-0.3 5 -0.2 300 1.6 - VDDx0.2 20 0.2 1.5 0.5 1 VSS-0.3 2 -0.2 200 1.0 - VDDx0.2 10 0.2 1.0 0.4 1 VSS-0.3 2 -0.2 100 .5 - VDDx0.2 10 0.2 0.75 0.30 1 V A A A mA mA/ MHz A Ioh Iol Address, Data, E, MLB, MX, RWB, VDA, VPA, VPB Output Low Voltage (Vol=VSS+0.4V) Idd Isby Address, Data, E, MLB, MX, RWB, VDA, VPA, VPB Supply Current (no load) Supply Current (core) Standby Current (No Load, Data Bus = VSS or VDD) ABORTB, BE, IRQB, NMIB, RESB, PHI2=VDD Capacitance (Vin=0V, TA=25C, f=1MHz) Cin Cts ABORTB, BE, IRQB, NMIB, PHI2, RBW, RESB, RDY, Address, Data, R/W - (Off state) * Not inspected during production test; verified on a sample basis. - 5 - 5 - 5 - 5 - 5 pF pF 1.2 1.1 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 0 1 MHz Operation@85C Typical 0.6u processed device x (With tester loading) * (CORE power only) x x VDD (VOLTS) x x * * * * 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.0 0 Typical 0.6u processed device @85C x x x x IDD (mA) 24 6 8 10 12 14 16 18 20 1 2 3 4 5 6 F Max (MHz) Table 5- 4 F Max vs. VDD VDD (VOLTS) Table 5-3 IDD vs. VDD The Western Design Center W65C816S 29 The Western Design Center, Inc. W65C816S Data Sheet Table 5-2 W65C816S AC Characteristics Symbol Parameter 5.0 +/- 5% 14MHz Min Max 3.3 +/- 10% 8MHz Min Max 3.0 +/- 5% 8MHz Min Max 2.5 +/- 5% 4MHz Min Max 1.8 +/- 5% 2MHz Min Max Units VDD tCYC tPWL tPWH tF,tR www..com tAH tADS tBH tBAS tACC tDHR tMDS tDHW tPCS tPCH tEH tES CEXT tBVD Cycle Time Clock Pulse Width Low Clock Pulse Width High Fall Time, Rise Time A0-A15 Hold Time A0-A15 Setup Time BA0-BA7 Hold Time BA0-BA7 Setup Time Access Time Read Data Hold Time Write Data Delay Time Write Data Hold Time Processor Control Setup Time Processor Control Hold Time E, MX Output Hold Time E, MX Output Setup Time Capacitive Load (1) be TO Valid Data (2) 4.75 70 35 35 10 10 30 10 10 10 10 10 - 5.25 DC 5 30 33 30 5 35 25 3.0 125 63 62 10 10 70 10 10 15 10 15 - 3.6 DC 5 40 40 40 5 35 30 2.85 125 63 62 10 10 70 10 10 15 10 15 - 3.15 DC 5 40 40 40 5 35 30 2.375 250 125 125 20 20 130 20 20 30 20 30 - 2.675 DC 5 75 75 70 5 35 60 1.71 500 250 250 40 40 365 40 40 60 40 60 - 1.89 DC 5 150 150 140 5 35 120 V nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS Pf nS 1. Test or loading on all outputs. 2. BE to High Impedance State is not testable but should be the same amount of time as BE to Valid Data. The Western Design Center W65C816S 30 The Western Design Center, Inc. W65C816S Data Sheet tF tR PHI2 tPWL www..com tPWH tAH see note 1 tAH RWB, SYNC VPB, MLB A0-A15 tADS Read Data tDHR Write Data tDHW tMDS Write Data tACC tDSR tDHR tDHW IRQB, NMIB, RESB, RDY ABORTB tPCS M/X M IEH tES E X X tPCH tPCS M tEH M tEH tES tEH BE Data tBVD Figure 5-1 General Timing Diagram 1. Timing measurement points are 50% VDD. The Western Design Center W65C816S 31 The Western Design Center, Inc. W65C816S Data Sheet 6 OPERATION TABLES Table 6-1 W65C816S Instruction Set-Alphabetical Sequence (continued on following page) 1. ADC 2. AND 3. ASL 4. BCC 5. BCS 6. BEQ www..com 7. BIT 8. BMI 9. BNE 10. BPL 11. BRA 12. BRK 13. BRL 14. BVC 15. 16. 17. 18. 19. 20. 21. 22. 23. 24. 25. 26. 27. 28. 29. BVS CLC CLD CLI CLV CMP COP CPX CPY DEC DEX DEY EOR INC INX Add Memory to Accumulator with Carry "AND" Memory with Accumulator Shift One Bit Left, Memory or Accumulator Branch on Carry Clear (C=0) Branch on Carry Set (C=1) Branch if Equal (Z=1) Bit Test Branch if Result Minus (N=1) Branch if Not Equal (Z=0) Branch if Result Plus (N=0) Branch Always Force Break Branch Always Long Branch on Overflow Clear (V=0) Branch on Overflow Set (V=1) Clear Carry Flag Clear Decimal Mode Clear Interrupt Disable Bit Clear Overflow Flag Compare Memory and Accumulator Coprocessor Compare Memory and Index X Compare Memory and Index Y Decrement Memory or Accumulator by One Decrement Index X by One Decrement Index Y by One "Exclusive OR" Memory with Accumulator Increment Memory or Accumulator by One Increment Index X by One 30. 31. 32. 33. 34. 35. 36. 37. 38. 39. 40. 41. 42. 43. 44. 45. 46. 47. 48. 49. 50. 51. 52. 53. 54. 55. 56. 57. 58. INY JML JMP JSL JSR LDA LDX LDY LSR MVN MVP NOP ORA PEA PEI PER PHA PHB PHD PHK PHP PHX PHY PLA PLB PLD PLP PLX PLY Increment Index Y by One Jump Long Jump to New Location Jump Subroutine Long Jump to News Location Saving Return Load Accumulator with Memory Load Index X with Memory Load Index Y with Memory Shift One Bit Right (Memory or Accumulator) Block Move Negative Block Move Positive No Operation "OR" Memory with Accumulator Push Effective Absolute Address on Stack (or Push Immediate Data on Stack) Push Effective Absolute Address on Stack ( Or Push Direct Data on Stack) Push Effective Program Counter Relative Address on Stack Push Accumulator on Stack Push Data Bank Register on Stack Push Direct Register on Stack Push Program Bank Register on Stack Push Processor Status on Stack Push Index X on Stack Push Index Y on Stack Pull Accumulator from Stack Pull Data Bank Register from Stack Pull Direct Register from Stack Pull Processor Status from Stack Pull Index X from Stack Pull Index Y from Stack The Western Design Center W65C816S 32 The Western Design Center, Inc. W65C816S Data Sheet 59. 5 REP 60. 61. 62. 63. 64. 65. 66. 67. 68. 69. 70. 71. 72. 73. 74. 75. ROL ROR RTI RTL RTS SBC SEP SEC SED SEI STA STP STX STY STZ TAX Reset Status Bits Rotate One Bit Left (Memory or Accumulator) Rotate One Bit Right (Memory or Accumulator) Return from Interrupt Return from Subroutine Long Return from Subroutine Subtract Memory from Accumulator with Borrow Set Processor Status Bit Set Carry Flag Set Decimal Mode Set Interrupt Disable Status Store Accumulator in Memory Stop the Clock Store Index X in Memory Store Index Y in Memory Store Zero in Memory Transfer Accumulator in Index X 76. 77. 78. 79. 80. 81. 82. 83. 84. 85. 86. 87. 88. 89. 90. 91. 92. TAY TCD TCS TDC TRB TSB TSC TSX TXA TXS TXY TYA TYX WAI WDM XBA XCE Transfer Accumulator to Index Y Transfer C Accumulator to Direct Register Transfer C Accumulator to Stack Pointer Register Transfer Direct Register to C Accumulator Test and Reset Bit Test and Set Bit Transfer Stack Pointer Register to C Accumulator Transfer Stack Pointer Register to Index X Transfer Index X to Accumulator Transfer Index X to Stack Pointer Register Transfer Index X to Index Y Transfer Index Y to Accumulator Transfer Index Y to Index X Wait for Interrupt Reserved for future use Exchange B and A Accumulator Exchange Carry and Emulation Bits www..com The Western Design Center W65C816S 33 The Western Design Center, Inc. W65C816S Data Sheet Table 6-2 Emulation Mode Vector Locations (8-bit Mode) Address 00FFFE,F 00FFFC,D 00FFFA,B 00FFF8,9 00FFF6,7 00FFF4,5 00FFF2,3 00FFF0,1 Label IRQB/BRK RESETB NMIB ABORTB (Reserved) COP (Reserved) (Reserved) Function Hardware/Software Hardware Hardware Hardware Hardware Software www..com Table 6-3 Native Mode Vector Locations (16-bit Mode) Address 00FFFE,F 00FFFC,D 00FFFA,B 00FFF8,9 00FFF6,7 00FFF4,5 00FFF2,3 00FFF0,1 Label IRQB (Reserved) NMIB ABORTB BRK COP (Reserved) (Reserved) Function Hardware Hardware Software Software The VP output is low during the two cycles used for vector location access. When an interrupt is executed, D=0 and I=1 in Status Register P. The Western Design Center W65C816S 34 The Western Design Center, Inc. W65C816S Data Sheet Table 6-4 OpCode Matrix M S D 0 BRK s 0 7,2 BPL r 1 2,2 JSR a 2 6,3 BMI r 3 www..com 2,2 RTI s 4 7,1 BVC r 5 2,2 RTS s 6 6,1 BVS r 7 2,2 BRA r 8 2,2 ! BCC r 9 2,2 LDY # A 2,2 BCS r B 2,2 CPY # C 2,2 BNE r D 2,2 CPX # E 2,2 BEQ r F 2,2 0 1 ORA(d,x) 6,2 ORA(d),y 5,2 AND(d,x) 6,2 AND(d),y 5,2 EOR(d,x) 6,2 EOR (d),y 5,2 ADC(d,x) 6,2 ADC(d),y 5,2 STA(d,x) 6,2 STA(d),y 6,2 LDA (d,x) 6,2 LDA (d),y 5,2 CMP (d,x) 6,2 CMP (d),y 5,2 SBC (d,x) 6,2 SBC (d),y 5,2 1 2 COP s 7,2 * ORA(d) 5,2 ! JSL al 8,4 * AND(d) 5,2 ! WDM 2,2 * EOR (d) 5,2 ! PER s 6,3 * ADC(d) 5,2 ! BRL rl 3,3 * STA (d) 5,2 ! LDX # 2,2 LDA (d) 5,2 ! REP # 3,2 * CMP (d) 5,2 ! SEP # 3,2 * SBC (d) 5,2 ! 2 3 ORA d,s 4,2 * ORA(d,s),y 7,2 * AND d,s 4,2 * AND(d,s),y 7,2 * EOR d,s 4,2 * EOR(d,s),y 7,2 * ADC d,s 4,2 * ADC(d,s),y 7,2 * STA d,s 4,2 * STA(d,s),y 7,2 * LDA d,s 4,2 * LDA(d,s),y 7,2 * CMP d,s 4,2 * CMP(d,s),y 7,2 * SBC d,s 4,2 * SBC(d,s),y 7,2 * 3 4 TBS d 5,2 ! TRB d 5,2 ! BIT d 3,2 BIT d,x 4,2 ! MVP xyc 7,3 * MVN xyc 7,3 * STZ d 3,2 ! STZ d,x 4,2 ! STY d 3,2 STY d,x 4,2 LDY d 3,2 LDY d,x 4,2 CPY d 3,2 PEI s 6,2 * CPX d 3,2 PEA s 5,3 * 4 5 ORA d 3,2 ORA d,x 4,2 AND d 3,2 AND d,x 4,2 EOR d 3,2 EOR d,x 4,2 ADC d 3,2 ADC d,x 4,2 STA d 3,2 STA d,x 4,2 LDA d 3,2 LDA d,x 4,2 CMP d 3,2 CMP d,x 4,2 SBC d 3,2 SBC d,x 4,2 5 6 ASL d 5,2 * ASL d,x 6,2 * ROL d 5,2 * ROL d,x 6,2 * LSR d 5,2 * LSR d,x 6,2 * ROR d 5,2 * ROR d,x 6,2 * STX d 3,2 * STX d,y 4,2 * LDX d 3,2 * LDX d,y 4,2 * DEC d 5,2 * DEC d,x 6,2 * INC d 5,2 * INC d,x 6,2 * 6 M S D 8 PHP s 3,1 CLC i 2,1 PLP s 4,1 SEC i 2,1 PHA s 3,1 CLI i 2,1 PLA s 4,1 SEI i 2,1 DEY i 2,1 TYA i 2,1 TAY i 2,1 CLV i 2,1 INY i 2,1 CLD i 2,1 INX i 2,1 SED i 2,1 8 9 ORA# 2,2 ORA a,y 4,3 AND# 2,2 AND a,y 4,3 EOR # 2,2 EOR a,y 4,3 ADC# 2,2 ADC a,y 4,3 BIT # 2,2 ! STA a,y 5,3 LDA# 2,2 LDA a,y 4,3 CMP # 2,2 CMP a,y 4,3 SBC # 2,2 SBC a,y 4,3 9 A ASL A 2,1 INC A 2,1 ! ROL A 2,1 DEC A 2,1 ! LSR A 2,1 PHY s 3,1 ! ROR A 2,1 PLY s 4,1 TXA i 2,1 TXS i 2,1 TAX i 2,1 TSX i 2,1 DEX i 2,1 PHX s 3,1 ! NOP i 2,1 PLX s 4,1 ! A B PHD s 4,1 * TCS i 2,1 * PLD s 5,1 * TSC i 2,1 * PHK s 3,1 * TCD i 2,1 * RTL s 6,1 * TDC i 2,1 * PHB s 3,1 * TXY i 2,1 * PLB s 4,1 * TYX i 2,1 * WAI i 3,1 ! STP i 3,1 ! XBA i 3,1 * XCE i 2,1 * B C TSB a 6,3 ! TRB a 6,3 ! BIT a 4,3 BIT a,x 4,3 ! JMP a 3,3 JMP al 4,4 * JMP (a) 5,3 JMP(a,x) 6,3 ! STY a 4,3 STZ a 3,4 ! LDY a 4,3 LDY a,x 4,3 CPY a 4,3 JML (a) 6,3 * CPX a 4,3 JSR (a,x) 6,3 * C D ORA a 4,3 ORA a,x 4,3 AND a 4,3 AND a,x 4,3 EOR a 4,3 EOR a,x 4,3 ADC a 4,3 ADC a,x 4,3 STA a 4,3 STA a,x 5,3 LDA a 4,3 LDA a,x 4,3 CMP a 4,3 CMP a,x 4,3 SBC a 4,3 SBC a,x 4,3 D E ASL a 6,3 ASL a,x 7,3 ROL a 6,3 ROL a,x 7,3 LSR a 6,3 LSR a,x 7,3 ROR a 6,3 ROR a,x 7,3 STX a 4,3 STZ a,x 5,3 ! LDX a 4,3 LDX a,y 4,3 DEC a 6,3 DEC a,x 7,3 INC a 6,3 INC a,x 7,3 E F ORA al 5,4 * ORA al,x 5,4 * AND al 5,4 * AND al,x 5,4 * EOR al 5,4 * EOR al,x 5,4 * ADC al 5,4 * ADC al,x 5,4 * STA al 5,4 * STA al,x 5,4 * LDA al 5,4 * LDA al,x 5,4 * CMP al 5,4 * CMP al,x 5,4 * SBC al 5,4 * SBC al,x 5,4 * F 0 1 2 3 4 5 6 7 8 9 A B C D E F LSD 7 ORA [d] 6,2 ORA[d],y 6,2 AND [d] 6,2 AND[d],y 6,2 EOR [d] 6,2 EOR[d].y 6,2 ADC[d] 6,2 ADC[d],y 6,2 STA[d] 6,2 STA[d],y 6,2 LDA [d] 6,2 LDA[d],y 6,2 CMP [d] 6,2 CMP[d],y 6,2 SBC [d] 6,2 SBC[d],y 6,2 7 * = Old instruction with new addressing modes ! = New Instruction The Western Design Center W65C816S 35 The Western Design Center, Inc. W65C816S Data Sheet Table 6-5 Operation, Operation Codes, and Status Register (continued on following 4 pages) Operation Mnemonic + Add - Subtract ^ AND (d,s),y (d,x) (d),y [d],y (a,x) d,x d,y (d) [d] a,x a,y d,s (a) A al rl d # a s i r Processor Status Code v OR v Exclusive OR www..com ADC A+M+CA AND ASL BCC BCS BEQ BIT BMI BNE BPL BRA BRK BRL* BVC BVS CLC CLD CLI CLV CMP COP* xyc al,x 7 N N N N 6 V V . . . . . M6 5 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 B 3 D . . . . . . . . . . . 0 . . . . 0 . . . 0 . . . . . . . . . . . 2 1 1 Z Z Z Z . . . Z . . . . . . . . . . . . Z . 0 C C . C . . . . . . . . . . . . 0 . . . C . 1 6D 2D 0E 2 3 7D 4 79 39 5 6F 2F 6 7F 3F 7 17 8 9 65 25 06 10 63 23 11 75 36 16 12 13 72 32 14 67 27 15 73 33 16 61 91 17 71 31 18 77 37 19 20 21 22 23 24 69 29 A^MA C15/7 6 5 4 3 2 10 0 3E 0A 1E Branch if C = 0 Branch if C = 1 Branch if Z = 1 A ^ M (Note 1) Branch if N = 0 Branch if Z = 0 Branch if N = 0 Branch Always Break (Note 2) Branch Long Always Branch if V = 0 Branch if V = 1 C0 0 D 0 1 0 V A-M Co-Processor CD DD 90 B0 F0 2C 3C 24 34 30 D0 . . . 89 M7 . . . . 00 82 . . . . . . . . C9 02 N . . . . . . . . . . . . 0 . . 10 80 * . . . . . . . . . 1 . . . . . 0 . . 1 50 70 18 D8 58 B8 D9 CF DF C5 C3 D5 D2 C7 D3 C1 D1 D7 The Western Design Center W65C816S 36 The Western Design Center, Inc. W65C816S Data Sheet Table 6-5 (continued) Operation + Add Mnemonic - Subtract ^ AND (d,s),y (d,x) (d),y xyc al,x d,x d,y (d) [d] a,x a,y d,s (a) al A rl v OR a v Exclusive OR CPX X-M 1 EC CC CE 3A DE Processor Status Code [d],y (a,x) 7 # 24 E0 C0 6 V . . . . . . . . . 5 1 . . . . . . . . . 4 B . . . . . . . . . 3 D . . . . . . . . . 2 I . . . . . . . . . 1 Z Z Z Z Z Z Z Z Z Z 0 C C C . . . . . . . d 2 3 4 5 6 7 8 9 E4 C4 C6 10 11 12 13 14 15 16 17 18 19 20 21 22 s r i 23 N N N N www..com CPY Y-M DEC DEX DEY EOR INC INX INY JML* JMP JSL JSR LDA LDX LDY LSR MVN* MVP* Decrement X-1 A Y-1 Y A v M A Increments X+1 X Y+1 Y Jump Long to new location Jump to new location Jump long to Subroutine Jump to Subroutine MA MX MY 0 15/7 6 5 4 3 2 1 0 C D6 CA 88 N N 49 N N 4D 5D 59 4F 5F 5D 45 43 55 52 47 53 41 51 57 EE 1A FE E6 F6 E8 C8 N N DC 4C 5C 22 20 AD AE AC 4E 4A BC 5E BD B9 BE AF BF FC A5 A6 A4 46 B4 56 54 44 EA 0D 1D 19 0F 1F 05 03 15 12 07 13 01 11 17 09 A3 B5 B6 B2 A7 B3 A1 B1 B7 A9 A2 A0 6C 7C . . . . N N . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Z Z . . . . . . N 0 . . . N . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Z Z . . . Z . C . . . . MM NEGATIVE MM POSITIVE No Operation AVMA NOP ORA The Western Design Center W65C816S 37 The Western Design Center, Inc. W65C816S Data Sheet Table 6-5 (continued) Operation Mnemonic + Add - Subtract ^ AND (d,s),y (d,x) (d),y [d],y (a,x) Processor Status Code v OR v Exclusive OR Mpc+1, Mpc+2 www..com ? Ms-1, Ms PEA* S-2 ? S xyc al,x d,x d,y (d) [d] a,x a,y d,s (a) A al 7 24 # N . . . . . . . . . . N N N N N N C2 N N N 6 V . . . . . . . . . . . . . V . . V . . V . 5 1 . . . . . . . . . . . . . M . . M . . M . 4 B . . . . . . . . . . . . . X . . X . . X . 3 D . . . . . . . . . . . . . D . . D . . D . 2 I . . . . . . . . . . . . . 1 . . 1 . . 1 . 1 Z . . . . . . . . . . Z Z Z Z Z Z Z Z Z Z . 0 C . . . . . . . . . . . . . C . rl 21 d a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 s 22 F4 D4 62 48 8B 0B 4B 08 DA 5A 68 AB 2B 28 FA 7A i r 23 PEI* PER* PHA PHB PHD* PHK* PHP PHX PHY PLA PLB PLD PLP PLX PLY REP ROL ROR RTI RTL M(d), M(d+1) ? Ms-1, Ms S-2 ? S Mpc+rl, Mpc+rl+1 ? Ms-1, Ms S-2 ? S A Ms, S-1 S DBR ? Ms, S-1 ? S D ? Ms, Ms-1, S-2 ? S PBR ? Ms, S-1 ? S P Ms, S-1 S X Ms, S-1 S Y Ms, S-1 S S + 1 S, Ms A S + 1 S, Ms DBR S + 2 S, Ms - 1, Ms ? D S + 1 S, Ms P S + 1 S, Ms X S + 1 S, Ms Y M^P P C 15/7 6 5 4 3 2 1 0 C C 15/7 6 5 4 3 2 1 0 C C C C C . 2E 6E 2A 6A 3E 7E 26 66 36 76 40 6B Return from Interrupt Return from Sub. Long N . The Western Design Center W65C816S 38 The Western Design Center, Inc. W65C816S Data Sheet Table 6-5 (continued) Operation + Add Mnemonic Processor Status Code - Subtract ^ AND (d,s),y (d,x) (d),y [d].y (a,x) d,x d,y (d) [d] a,x a,y d,s (a) A al rl d # a s v OR v Exclusive OR RTS SBC SEC SED SEI SEP STA STP STX STY STZ TAX TAY TCD TCS TDC TRB TSB TSC TSX TXA AVM M S? C SX X A Return from Subroutine A - M - (C) A 1C 1 D 1? 1 ED FD F9 FF E5 E3 F5 F2 E7 F3 E1 F1 F7 38 F8 78 E2 8D 9D 8F 9F 85 83 95 92 87 93 81 91 97 DB 8E 8C 9C 9E 86 84 64 94 74 AA AB 5B 1B 7B 1C 0C 3B BA 8A 14 04 96 xyc al,x 7 N . E9 N . . . N . . . . . N N N . N . . N N N 6 V . . . . . V . . . . . . . . . . . . . . . 5 M . . . . . M . . . . . . . . . . . . . . . 4 X . . . . . X . . . . . . . . . . . . . . . 3 D . . . 1 . D . . . . . . . . . . . . . . . 2 1 . . . . 1 1 . . . . . . . . . . . . . . . 1 Z . Z . . . Z . . . . . Z Z Z . Z Z Z Z Z Z 0 C . C 1 . . C . . . . . . . . . . . . . . . r 20 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 i 21 22 60 23 24 www..com MVP P AM STOP (1 PHI2) X M YM 00 M AX A Y CD CS DC The Western Design Center W65C816S 39 The Western Design Center, Inc. W65C816S Data Sheet Table 6-5 (continued) Operation + Add Mnemonic Processor Status Code - Subtract ^ AND (d,s),y (d,x) (d),y [d].y (a,x) d,x d,y (d) [d] a,x a,y d,s (a) A al rl d # a s v OR v Exclusive OR TXS X S xyc al,x 7 N . N N N . . N . 6 V . . . . . . . . 5 M . . . . . . . . 4 X . . . . . . . . 3 D . . . . . . . . 2 1 . . . . . . . . 1 Z . Z Z Z . . Z . 0 C . . . . . . . E i 19 r 20 1 2 9A 9B 98 BB CB 42 EB FB 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 21 22 23 24 www..com TXY X Y TYA TYX WAI WDM XBA XCE Y A YX 0 RDY No Operation (Reserved) B? C? A E Notes: 1. Bit immediate N and V flags not affected. When M=0, M 15 N and M 14 V. 2. Break Bit (B) in Status register indicates hardware or software break. = New W65C816 instructions The Western Design Center W65C816S 40 The Western Design Center, Inc. W65C816S Data Sheet Table 6-6 Addressing Mode Symbol Table Symbol # A r rl I s d d,x d,y (d) (d,x) (d),y Addressing Mode immediate accumulator program counter relative program counter relative long implied stack direct direct indexed with x direct indexed with y direct indirect direct indexed indirect direct indirect indexed Symbol [d] [d],y a a,x a,y al al,x d,s (d,s),y (a) (a,x) xyc Addressing Mode direct indirect long direct indirect long indexed absolute absolute indexed with x absolute indexed with y absolute long absolute long indexed stack relative stack relative indirect indexed absolute indirect absolute indexed indirect block move www..com The Western Design Center W65C816S 41 The Western Design Center, Inc. W65C816S Data Sheet Table 6-76-6 Instruction Operation (continued on following 6 pages) Address Mode 1a. Absolute a ADC, AND, BIT, CMP, CPX, CPY, EOR, LDA, LDX LDY ORA, SBC, STA, STX, STY, STZ, 18 OpCodes, 3 bytes, 4 & 5 cycles 1b. Absolute a JMP (4C) 1 OpCode, 3 bytes, 3 cycles www..com 1c. Absolute a JSR 1 OpCode, 3 bytes, 6 cycles (different order from N6502) Note Cycle 1 2 3 4 4a 1 2 3 1 1 2 3 4 5 6 1 1 2 3 4 4a 5 6a 6 1 2 3 4 5 6 1 1 2 3 4 5 6 7 8 1 1 2 3 4 5 6 1 1 2 3 4 5 1 VPB 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 MLB 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VDA (14) 1 0 0 1 1 1 0 0 1 1 0 0 0 1 1 1 1 0 0 1 1 0 1 1 1 0 0 0 0 0 1 1 0 1 1 0 0 0 0 1 1 0 0 1 1 1 1 1 0 0 1 1 1 VPA (14) 1 1 1 0 0 1 1 1 1 1 1 1 0 0 0 1 1 1 1 0 0 0 0 0 1 1 1 0 1 1 1 1 1 0 0 1 0 1 1 1 1 1 1 0 0 0 1 1 1 1 0 0 1 Address Bus (15) PBR,PC PBR,PC+1 PBR,PC+2 DBR,AA DBR,AA+1 PBR,PC PBR,P C+1 PBR,PC+2 PBR,New PC PBR,PC PBR,PC+1 PBR,PC+2 PBR,PC+2 0,S 0,S-1 PBR,NEWPC PBR,PC PBR,PC+1 PBR,PC+2 DBR,AA DBR,AA+1 DBR,AA+1 DBR,AA+1 DBR,AA PBR,PC PBR-PC+1 PBR-PC+2 PBR,PC+2 PBR,AA+X PBR,AA+X+1 PBR,NEW PC PBR,PC PBR,PC+1 0,S 0,S-1 PBR,PC+2 PBR,PC+2 PBR,AA+X PBR,AA+X+1 PBR,NEW PC PBR,PC PBR,PC+1 PBR,PC+2 0,AA 0,AA+1 0,AA+2 NEW PBR,PC PBR,PC PBR,PC+1 PBR,PC+2 0,AA 0,AA+1 PBR,NEW PC Data Bus OpCode AAL AAH Data Low Data High OpCode New PCL New PCH OpCode OpCode New PCL New PCH IO PCH PCL Next OpCode OpCode AAL AAH Data Low Data High IO Data High Data Low OpCode AAL AAH IO New PCL New PCH OpCode OpCode AAL PCH PCL AAH IO New PCL New PCH Next OpCode OpCode AAL AAH New PCL New PCH New PBR OpCode OpCode AAL AAH New PCL New PCH OpCode RWB 1 1 1 1/0 1/0 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 (1) 1d. Absolute (R-M-W) a ASL, DEC, INC, LSR, ROL, ROR, TRB, TSB 6 OpCodes, 3 bytes, 6 & 8 cycles (1) (3)(17) (1) 2a. Absolute Indexed Indirect (a,x) JMP 1 OpCode, 3 bytes, 6 cycles 2b. Absolute Indexed Indirect (a,x) JSR 1 OpCode, 3 bytes, 8 cycles 3a. Absolute Indirect (a) JML 1 OpCode, 3 bytes, 6 cycles 3b. Absolute Indirect (a) JMP 1 OpCode, 3 bytes, 5 cycles (See Table 6.8 for abbreviations.) The Western Design Center W65C816S 42 The Western Design Center, Inc. W65C816S Data Sheet Table 6-7 (continued) Address Mode 4a. Absolute Long al ADC, AND, CMP, EOR, LDA, ORA, SBC, STA, 8 OpCodes, 4 bytes, 5 & 6 cycles (1) 4b. Absolute Long (JUMP) al JMP 1 OpCode, 4 bytes, 4 cycles www..com Note Cycle 1 2 3 4 5 5a 1 2 3 4 1 1 2 3 4 5 6 7 8 1 1 2 3 4 5 5a 1 2 3 3a 4 4a 1 2 3 4 5 5a 6 7a 7 1 2 3 3a 4 4a 1 2 VPB 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 MLB 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 1 1 1 4c. Absolute Long (JUMP to Subroutine Long) al JSL 1 OpCode, 4 bytes, 7 cycles 5. Absolute Long,X al,x ADC, AND, CMP, EOR, LDA, ORA, SBC, STA 8 OpCodes, 4 bytes, 5 and 6 cycles (1) 6a Absolute, X a, x ADC, AND, BIT, CMP, EOR, LDA, LDY, ORA, SBC, STA, STA, STZ 12 OpCodes, 3 bytes, 4,5 and 6 cycles 6b Absolute, X(R-M-W) a,x ASL, DEC INC LSR ROL, ROR 6 OpCodes, 3 bytes, 7 and 9 cycles (1) (3)(17) (1) 7. Absolute, Y a,y ADC, AND, CMP, EOR, LDA, LDX, ORA, SBC, STA 9 OpCodes, 3 bytes, 4,5 and 6 cycles (4) (1) (4) (1) VDA (14) 1 0 0 0 1 1 1 0 0 0 1 1 0 0 1 0 0 1 1 1 1 0 0 0 1 1 1 0 0 0 1 1 1 0 0 0 1 1 0 1 1 1 0 0 0 1 1 1 0 VPA (14) 1 1 1 1 0 0 1 1 1 1 1 1 1 1 0 0 1 0 0 1 1 1 1 1 0 0 1 1 1 0 0 0 1 1 1 0 0 0 0 0 0 1 1 1 0 0 0 1 0 Address Bus (15) PBR,PC PBR,PC+1 PBR,PC+2 PBR,PC+3 AAB,AA AAB,AA+1 PBR,PC PBR,PC+1 PBR,PC+2 PBR,PC+3 New PBR,PC PBR,PC PBR,PC+1 PBR,PC+2 0,S 0,S PBR,PC+3 0,S-1 0,S-2 New PBR,PC PBR,PC PBR,PC+1 PBR,PC+2 PBR,PC+3 AAB,AA+X AAB,AA+X+1 PBR,PC PBR,PC+1 PBR,PC+2 DBR,AAH,AAL+XL Data Bus OpCode AAL AAH AAB Data Low Data High OpCode New PCL New PCH New BR OpCode OpCode New PCL New PCH PBR IO New PBR PCH PCL Next OpCode OpCode AAL AAH AAB Data Low Data High OpCode AAL AAH IO Data Low Data High OpCode AAL AAH IO Data Low Date High IO Data High Data Low OpCode AAL AAH IO Data Low Data High OpCode IO RWB 1 1 1 1 1/0 1/0 1 1 1 1 1 1 1 1 0 1 1 0 0 1 1 1 1 1 1/0 1/0 1 1 1 1 1/0 1/0 1 1 1 1 1 1 1 0 0 1 1 1 1 1/0 1/0 1 1 DBR,AA+X DBR,AA+X+1 PBR,PC PBR,PC+1 PBR,PC+2 DBR,AAH,AAL+XL DBR,AA+X DBR,AA+X+1 DBR,AA+X+1 DBR,AA+X+1 DBR,AA+X PBR,PC PBR,PC+1 PBR,PC+2 DBR,AAH,AAL+YL DBR,AA+Y DBR,AA+Y+1 PBR,PC PBR,PC+1 8. Accumulator A ASL, DEC, INC, LSR, ROL, ROR 6 OpCodes, 1 byte, 2 cycles (see Table 6-8 for abbreviations) The Western Design Center W65C816S 43 The Western Design Center, Inc. W65C816S Data Sheet Table 6-7 (continued) Address Mode 9a. Block Move Negative (backward) xyc MVN 1 Op Code 3 bytes 7 cycles x=Source Address y=Destination c=# of bytes to move-1 x,y Increment www..com FFFFFF Source End Dest. End Source Start Dest. Start 000000 Note Cycle 1 2 3 4 5 6 7 1 2 3 4 5 6 7 1 2 3 4 5 6 7 1 1 2 3 4 5 6 7 1 2 3 4 5 6 7 1 2 3 4 5 6 7 1 VPB 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 MLB 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 N-2 Byte C=2 N Byte C=0 9b. Block Move Positive (forward) xyc (MVP) 1 Op Code 3 bytes 7 cycles x=Source Address y=Destination c=# of bytes to move-1 x,y Decrement MVP is used when the destination start address is higher (more positive ) than the source start address. FFFFFF Destination. Start Source Start Destination. End N-2 Byte C=2 N-1 Byte C=1 N Byte Last C=0 000000 VDA (14) 1 0 0 1 1 0 0 1 0 0 1 1 0 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 0 1 1 0 0 1 0 0 1 1 0 0 1 VPA (14) 1 1 1 0 0 0 0 1 1 1 0 0 0 0 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 0 0 0 0 1 1 1 0 0 0 0 1 Address Bus (15) PBR,PC PBR,PC+1 PBR,PC+2 SBA,X DBA,Y DBA,Y DBA,Y PBR,PC PBR,PC+1 PBR,PC+2 SBA,X+1 DBA,Y+1 DBA,Y+1 DBA,Y+1 PBR,PC PBR,PC+1 PBR,PC+2 SBA,X+2 DBA,Y+2 DBA,Y+2 DBA,Y+2 PBR,PC+3 PBR,PC PBR,PC+1 PBR,PC+2 SBA,X DBA,Y DBA,Y DBA,Y PBR,PC PBR,PC+1 PBR,PC+2 SBA,X-1 DBA,Y-1 DBA,Y-1 DBA,Y-1 PBR,PC PBR,PC+1 PBR,PC+2 SBA,X-2 DBA,Y-2 DBA,Y-2 DBA,Y-2 PBR,PC+3 Data Bus OpCode DBA SBA SRC Data Dest Data IO IO OpCode DBA SBA SRC Data Dest Data IO IO OpCode DBA SBA SRC Data Dest Data IO IO Next OpCode OpCode DBA SBA SRC Data Dest Data IO IO OpCode DBA SBA SRC Data Dest Data IO IO OP Code DBA SBA SRC Data Dest Data IO IO Next OpCode RWB 1 1 1 1 0 1 1 1 1 1 1 0 1 1 1 1 1 1 0 1 1 1 1 1 1 1 0 1 1 1 1 1 1 0 1 1 1 1 1 1 0 1 1 1 (see Table 6-7 for abbreviations) The Western Design Center W65C816S 44 The Western Design Center, Inc. W65C816S Data Sheet Table 6-7 (continued) Address Mode 10a. Direct d ADC AND BIT, CMP, CPX, CPY ,EOR, LDA, LDX, LDY, ORA, SBC, STA, STX, STY, STZ 16 OpCodes, 2 bytes, 3, 4 & 5 cycles 10b. Direct (R-M-W)d ASL, DEC, INC, LSR, ROL, ROR, TRB, TSB, 8 OpCodes, 2 bytes, 5,6,7 and 8 cycles www..com Note Cycle 1 2 2a 3 3a 1 2 2a 3 3a 4 5a 5 1 2 2a 3 4 5 6 6a 1 2 2a 3 4 5 5a 1 2 2a 3 4 4a 5 5a 1 2 2a 3 4 5 6 6a 1 2 2a 3 4 5 6 6a VPB 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 MLB 1 1 1 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 (2) (1) (2) (1) (3),(17) (1) 11. Direct Indexed Indirect (d,x) ADC, AND, CMP, EOR, LDA, ORA, SBC, STA, 8 OpCodes, 2 bytes, 6,7 and 8 cycles (2) (1) 12. Direct Indirect (d) ADC, AND, CMP, EOR, LDA, ORA, SBC. STA, 8 OpCodes 2 bytes, 5,6 and 7 cycles (2) (1) 13. Direct Indirect Indexed (d),y ADC, AND, CMP, EOR, LDA, ORA, SBC, STA 8 OpCodes, 2 bytes, 5,6,7 and 8 cycles VDA (14) 1 0 0 1 1 1 0 0 1 1 0 1 1 1 0 0 0 1 1 1 1 1 0 0 1 1 1 1 1 0 0 1 1 0 1 1 1 0 0 1 1 1 1 1 1 0 0 1 1 1 1 1 VPA (14) 1 1 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 Address Bus (15) PBR,PC PBR,PC+1 PBR,PC+1 0,D+DO 0,D+DO+1 PBR, PC PBR,PC+1 PBR,PC+1 0,D+DO 0,D+DO+1 0,D+DO+1 0,D+DO+1 0,D+DO PBR,PC PBR,PC+1 PBR,PC+1 PBR,PC+1 0,D+DO+X 0,D+DO+X+1 DBR,AA DBR,AA+1 PBR,PC PBR,PC+1 PBR,PC+1 0,D+DO 0,D+DO+1 DBR,AA DBR,AA+1 PBR,PC PBR,PC+1 PBR,PC+1 0,D+DO 0,D+DO+1 DBR,AAH.AAL+YL Data Bus OpCode DO IO Data Low Data High OpCode DO IO Data Low Data High IO Data High Data Low OpCode DO IO IO AAL AAH Data Low Data High OpCode DO IO AAL AAH Data Low Data High OpCode DO IO AAL AAH IO Data Low Data High OpCode DO IO AAL AAH AAB Dat a Low Data High OpCode DO IO AAL AAH AAB Data Low Data High RWB 1 1 1 1/0 1/0 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1/0 1/0 1 1 1 1 1 1/0 1/0 1 1 1 1 1 1 1/0 1/0 1 1 1 1 1 1 1/0 1/0 1 1 1 1 1 1 1/0 1/0 (2) (4) (1) 14. Direct Indirect Indexed Long [d],y ADC, AND, CMP, EOR, LDA, ORA, SBC, STA 8 OpCodes, 2 bytes, 6,7 and 8 cycles (2) (1) 15. Direct Indirect Long [d] ADC, AND, CMP, EOR, LDA, ORA, SBC, STA 8 OpCodes, 2 bytes, 6,7 and 8 cycles (2) (1) DBR,AA+Y DBR,AA+Y+1 PBR,PC PBR,PC+1 PBR,PC+1 0,D+DO 0,D+DO+1 0,D+DO+2 AAB,AA+Y AAB,AA+Y+1 PBR,PC PBR,PC+1 PBR,PC+1 0,D+DO 0,D+D0+1 0,D+DO+2 AAB,AA AAB,AA+1 (see Table 6-8 for abbreviations) The Western Design Center W65C816S 45 The Western Design Center, Inc. W65C816S Data Sheet Table 6-7 (continued) Address Mode 16a. Direct, X d,x ADC, AND, BIT, CMP, EOR, LDA LDY, ORA, SBC, STA, STY, STZ, 12 OpCodes,2 bytes, 4,5,and 6 cycles Note Cycle 1 2 2a 3 4 4a 1 2 2a 3 4 4a 5 6a 6 1 2 2a 3 4 4a 1 2 2a VPB 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 MLB 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 1 1 1 1 VDA (14) 1 0 0 0 1 1 1 0 0 0 1 1 0 1 1 1 0 0 0 1 1 1 0 0 VPA (14) 1 1 0 0 0 0 1 1 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 1 Address Bus (15) PBR,PC PBR,PC+1 PBR,PC+1 PBR,PC+1 0,D+DO+X 0,D+DO+X+1 PBR,PC PBR,PC+1 PBR,PC+1 PBR,PC+1 0,D+DO+X 0,D+DO+X+1 0,D+DO+X+1 0,D+DO+X+1 0,D+DO+X PBR,PC PBR,PC+1 PBR,PC+1 PBR,PC+1 0,D+DO+Y 0,D+DO+Y+1 PBR,PC PBR,PC+1 PBR,PC+2 Data Bus OpCode DO IO IO Data Low Data High OpCode DO IO IO Data Low Data High IO Data High Data Low OpCode DO IO IO Data Low Data High OpCode IDL IDH RWB 1 1 1 1 1/0 1/0 1 1 1 1 1 1 1 0 0 1 1 1 1 1/0 1/0 1 1 1 (2) (1) 16b. Direct, X (R-M-W) d,x ASL, DEC, INC, LSR, ROL, ROR, 6 OpCodes, 2 bytes, 6,7,8 and 9 cycles www..com (2) (1) (3),(17) (1) 17. Direct, Y d,y LDX, STX 2 OpCodes, 2 bytes, 4,5 and 6 cycles (2) (1) 18.Immediate # ADC, AND, BIT, CMP, CPX, CPY, EOR, LDA, LDX, LDY, ORA, REP, SEC, SEP 14 OpCodes, 2 and 3 bytes, 2 and 3 cycles 19a. Implied i CLC, CLD, CLI, CLV, DEX, DEY, INX, INY, NOP, SEC, SED, SEI, TAX, TAY, TCD, TCS, TDC, TSC, TSX, TXA, TXS, TXY, TYA, TYX, XCE 25 OpCodes, 1 byte, 2 cycles 19b. Implied i XBA 1 OpCode, 1 byte, 3 cycles 19c. Stop the Clock STP 1 OpCode 1 byte RESB=1 3 cycles RESB=0 RESB=0 RESB=1 (See 22a. Stack Hardware Interrupt) 19d. Wait for Interrupt WAI 1 OpCode,1 byte 3 cycles IRQB, NMIB (1)(6) 1 2 1 1 1 1 1 0 1 0 PBR,PC PBR,PC+1 OpCode IO 1 1 1 2 3 1 2 3 1c 1b 1a 1 RDY=1 (9)RDY=1 RDY=0 RDY=1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 0 0 0 0 0 1 1 0 0 1 1 0 0 1 0 0 0 0 0 1 1 0 0 1 PBR,PC PBR,PC+1 PBR,PC+1 PBR,PC PBR,PC+1 PBR,PC+1 PBR,PC+1 PBR,PC+1 PBR,PC+1 PBR,PC+1 PBR,PC PBR,PC+1 PBR,PC+1 PBR,PC+1 OpCode IO IO OpCode IO IO RES (BRK) RES (BRK) RES (BRK) BEGIN OpCode IO IO IRQ(BRK) 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 3 1 (see Table 6-8 for abbreviations The Western Design Center W65C816S 46 The Western Design Center, Inc. W65C816S Data Sheet Table 6-7 (continued) Address Mode 20. Relative r BCC, BCS, BEQ, BMI, BNE, BPL, BRA, BVC,BVS 9 OpCodes, 2 bytes, 2,3 and 4 cycles 21. Relative Long rl BRL 1 OpCode, 3 bytes, 4 cycles www..com 22a. Stack s ABORT, IRQ, NMI, RES 4 hardware interrupts 0 bytes, 7 and 8 cycles Note Cycle 1 2 2a 2b 1 1 2 3 4 1 1 2 3 4 5 6 7 8 1 1 2 3 4 4a 1 2 3a 3 1 2 3 4 5 1 2 2a 3 4 5 6 1 2 3 4 5 6 VPB 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 MLB 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 (5) (6) (3) (7) (10) (10) (10) (11) 22b. Stack s PLA, PLB, PLD, PLP, PLX, PLY Different than N6502 6 Op Codes,1 byte, 4 and 5 cycles (1) 22c. Stack s PHA, PHB PHP, PHD, PHK, PHX, PHY 7 Op Codes, 1 byte, 3 and 4 cycles 22d. Stack s PEA 1 Op Code, 3 bytes, 5 cycles (1) (12) 22e. Stack s PEI 1 Op Code, 2 bytes, 6 and 7 cycles (2) 22f. Stack s PER 1 Op Code, 3 bytes, 6 cycles VDA (14) 1 0 0 0 1 1 0 0 0 1 1 0 1 1 1 1 1 1 1 1 0 0 1 1 1 0 1 1 1 0 0 1 1 1 0 0 1 1 1 1 1 0 0 0 1 1 VPA (14) 1 1 0 0 1 1 1 1 0 1 1 0 0 0 0 0 0 0 1 1 0 0 0 0 1 0 0 0 1 1 1 0 0 1 1 0 0 0 0 0 1 1 1 0 0 0 Address Bus (15) PBR,PC PBR,PC+1 PBR,PC+1 PBR,PC+1 PBR,PC+Offset PBR,PC PBR,PC+1 PBR,PC+2 PBR,PC+2 PBR,PC+Offset PBR,PC PBR,PC 0,S 0,S-1 0,S-2 0.S-3 0,VA 0,VA+1 0,AAV PBR,PC PBR,PC+1 PBR,PC+1 0,S+1 0,S+2 PBR,PC PBR,PC+1 0,S 0,S-1 PBR,PC PBR,PC+1 PBR,PC+2 0,S 0,S-1 PBR,PC PBR,PC+1 PBR,PC+1 0,D+DO 0,D+DO+1 0,S 0,S-1 PBR,PC PBR,PC+1 PBR,PC+2 PBR,PC+2 0,S 0,S-1 Data Bus OpCode Offset IO IO OpCode OpCode Offset Low Offset High IO OpCode IO IO PBR PCH PCL P AAVL AAVH Next OpCode OpCode IO IO REG Low REG High OpCode IO REG High REG Low OpCode AAL AAH AAH AAL OpCode DO IO AAL AAH AAH AAL OpCode Offset Low Offset High IO PCH+Offset+Carry RWB 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 0 0 1 1 1 1 0 0 PCL+Offset (see Table 6-8 for abbreviations) The Western Design Center W65C816S 47 The Western Design Center, Inc. W65C816S Data Sheet Table 6-7 (continued) Address Mode 22g. Stack s RTI 1 Op Code, 1 byte, 6 and 7 cycles (different order fromN6502) Note Cycle 1 2 3 4 5 6 7 1 1 2 3 4 5 6 1 1 2 3 4 5 6 1 1 2 3 4 5 6 7 8 1 1 2 3 4 4a 1 2 3 4 5 6 7 7a VPB 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 MLB 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VDA (14) 1 0 0 1 1 1 1 1 1 0 0 1 1 0 1 1 0 0 1 1 1 1 1 0 1 1 1 1 1 1 1 1 0 0 1 1 1 0 0 1 1 0 1 1 VPA (14) 1 0 0 0 0 0 0 1 1 0 0 0 0 0 1 1 0 0 0 0 0 1 1 1 0 0 0 0 0 0 1 1 1 0 0 0 1 1 0 0 0 0 0 0 Address Bus (15) PBR,PC PBR,PC+1 PBR,PC+1 0,S+1 0,S+2 0,S+3 0,S+4 PBR,New PC PBR,PC PBR,PC+1 PBR,PC+1 0,S+1 0,S+2 0,S+2 PBR,PC PBR,PC PBR,PC+1 PBR,PC+1 0,S+1 0,S+2 0,S+3 NEW PBR,PC PBR,PC PBR,PC+1 0,S 0,S-1 0,S-2 0,S-3 (16) 0,VA 0,VA+1 0,AAV PBR,PC PBR,PC+1 PBR,PC+1 0,S+SO 0,S+SO+1 PBR,PC PBR,PC+1 PBR,PC+1 0,S+SO 0,S+SO+1 0,S+SO+1 DBR,AA+Y DBR,AA+Y+1 Data Bus OpCode IO IO P New PCL New PCH PBR Next OpCode OpCode IO IO PCL PCH IO OpCode OpCode IO IO New PCL New PCH New PBR Next OpCode OpCode Signature PBR PCH PCL P AAVL AAVH Next OpCode OpCode SO IO Data Low Data High OpCode SO IO AAL AAH IO Data Low Data High RWB 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1/0 1/0 1 1 1 1 1 1 1/0 1/0 (3) (7) 22h. Stack s RTS www..com 1 OpCode, 1 byte, 6 cycles 22i. Stack s RTL 1 Op Code, 1 byte, 6 cycles 22j. Stack s BRK,COP 2 OpCodes, 2 bytes 7 and 8 cycles (3) (7) (10) (10) (10) 23. Stack Relative d,s ADC, AND, CMP, EOR, LDA, ORA, SBC, STA 8 Op Codes, 2 bytes, 4 and 5 cycles (1) 24. Stack Relative Indirect Indexed (d,s),y ADC, AND, CMP, EOR, LDA, ORA, SBC, STA 8 Op Codes, 2 bytes, 7 and 8 cycles (1) (see Table 6-8 for abbreviations) The Western Design Center W65C816S 48 The Western Design Center, Inc. W65C816S Data Sheet Notes: Be aware that notes #4-7, 9 and 10 apply to the W65C02S and W65C816S. All other notes apply to the W65C816S only. Add 1 byte (for immediate only) for M=0 or X=0 (i.e. 16-bit data), add 1 cycle for M=0 or X=0. REP, SEP are always 3 cycle instructions and VPA is low during the third cycle. The address bus is PC+1 during the third cycle. 2. Add 1 cycle for direct register low (DL) not equal 0. 3. Special case for aborting instruction. This is the last cycle which may be aborted or the Status, PBR or DBRregisters will be updated. 4. Add 1 cycle for indexing across page boundaries, or write, or X=0. When X=1 or in the emulation mode, this cycle contains invalid addresses. www..comcycle if branch is taken. 5. Add 1 6. Add 1 cycle if branch is taken across page boundaries in 6502 emulation mode (E=1). 7. Subtract 1 cycle for 6502 emulation mode (E=1). 8. Add 1 cycle for REP, SEP. 9. Wait at cycle 2 for 2 cycles after NMIB or IRQB active input. 10. RWB remains high during Reset. 11. BRK bit 4 equals "0" in Emulation mode. 12. PHP and PLP. 13. Some OpCodes shown are compatible only with the W65C816S. 14. VDA and VPA are not valid outputs on the W65C02S but are valid on the W65C816S. The two signals, VDA and VPA, are included to point out the upward compatibility to the W65C816S. When VDA and VPA are both a one level, this is equivalent to SYNC being a one level. 15. The PBR is only applicable to the W65C816S. 16. COP Latches. 17. In the emulation mode, during a R-M-W instruction the RWB is low during both write and modify cycles. 1. The Western Design Center W65C816S 49 The Western Design Center, Inc. W65C816S Data Sheet Table 6-8 Abbreviations Abbreviation AAB AAH AAL AAVH AAVL C D DBA DBR DEST DO IDH IDL IO OFF P PBR PC PCH PCL R-M-W REG S SBA SRC SO VA x,y Explanation Absolute Address Bank Absolute Address High Absolute Address Low Absolute Address Vector High Absolute Address Vector Low Accumulator Direct Register Destination Bank Address Data Bank Address Destination Direct Offset Immediate Data High Immediate Data Low Internal Operation Offset Status Register Program Bank Register Program Counter Program Counter High Program Counter Low Read-Modify-Write Register Stack Address Source Bank Address Source Stack Offset Vector Address Index Register www..com The Western Design Center W65C816S 50 The Western Design Center, Inc. W65C816S Data Sheet PHI2 www..com E Q 8 BANK ADDRESS BA0-BA7 W65C816S Clock D OE 573 OR 373 CE D0-D7 BA0-BA7 R/WB B 8 DIR DATA BUS D0-D7 A 8 74X245 Figure 6-1 Bank Address Latching Circuit The Western Design Center W65C816S 51 The Western Design Center, Inc. W65C816S Data Sheet 7 RECOMMENDED W65C816S ASSEMBLER SYNTAX STANDARDS 7.1 Directives Assembler directives are those parts of the assembly language source program which give directions to the assembler; this includes the definition of data area and constants within a program. This standard excludes any definitions of assembler directives. www..com 7.2 Comments An assembler should provide a way to use any line of the source program as a comment. The recommended way of doing this is to treat any blank line, or any line that starts with a semi-colon or an asterisk as a comment. Other special characters may be used as well. 7.3 The Source Line Any line which causes the generation of a single W65C816S machine language instruction should be divided into four fields: a label field, the operation code, the operand, the comment field. 7.3.1 The Label Field The label field begins in column one of the line. A label must start with an alphabetic character, and may be followed by zero or more alphanumeric characters. An assembler may define an upper limit on the number of characters that can be in a label, so long as that upper limit is greater than or equal to six characters. An assembler may limit the alphabetic characters to upper-case characters if desired. If lower-case characters are allowed, they should be treated as identical to their upper-case equivalents. Other characters may be allowed in the label, so long as their use does not conflict with the coding of operand fields. 7.3.2 The Operation Code Field The operation code shall consist of a three character sequence (mnemonic) from Table 7-1. It shall start no sooner than column 2 of the line, or one space after the label if a label is coded. 7.3.2.1 Many of the operation codes in Table 6-1 have duplicate mnemonics; when two or more machine language instruction has the same mnemonic, the assembler resolves the difference based on the operand. 7.3.2.2 If an assembler allows lower-case letters in labels, it must also allow lower-case letters in the mnemonic. When lower-case letters are used in the mnemonic, they shall be treated as equivalent to the upper-case counterpart. Thus, the mnemonics LDA, lda and LdA must all be recognized, and are equivalent. 7.3.2.3 In addition to the mnemonics shown in Table 7-1, an assembler may provide the alternate mnemonics shown in Table 7-1. The Western Design Center W65C816S 52 The Western Design Center, Inc. W65C816S Data Sheet Table 7-1 Alternate Mnemonics WDC Standard BCC BCS CMP A DEC A INC A JSL JML TCD TCS TDC TSC XBA Alias BLT BGE CMA DEA INA JSR JMP TAD TAS TDA TSA SWA www..com 7.3.2.4 JSL should be recognized as equivalent to JSR when it is specified with a long absolute address forced. JML is equivalent to JMP with long addressing forced. 7.3.3 The Operand Field The operand field may start no sooner than one space after the operation code field. The assembler must be capable of at least twenty-four bit address calculations. The assembler should be capable of specifying addresses as labels, integer constants, and hexadecimal constants. The assembler must allow addition and subtraction in the operand field. Labels shall be recognized by the fact they start with alphabetic characters. Decimal numbers shall be recognized as containing only the decimal digits 0...9. Hexadecimal constants shall be recognized by prefixing the constant with a "$" character, followed by zero or more of either the decimal digits or the hexadecimal digits "A"..."F". If lower-case letters are allowed in the label field, then they shall also be allowed as hexadecimal digits. 7.3.3.1 All constants, no matter what their format, shall provide at least enough precision to specify all values that can be represented by a twenty- four bit signed or unsigned integer represented in two's complement notation. 7.3.3.2 Table 7-2 shows the operand formats that shall be recognized by the assembler. bol d is a label or value which the assembler can recognize as being less than $100. The symbol a is a label or value which the assembler can recognize as greater than $FF but less than $10000; the symbol al is a label or value that the assembler can recognize as being greater than $FFF. The symbol EXT is a label which cannot be located by the assembler at the time the instruction is assembled. Unless instructed otherwise, an assembler shall assume that EXT labels are two bytes long. The symbols r and rl are 8 and 16 bit signed displacements calculated by the assembler. The Western Design Center W65C816S 53 The Western Design Center, Inc. W65C816S Data Sheet Table 7-2 Address Mode Formats Addressing Mode Immediate Format #d #a #al #EXT # Absolute Indexed by Y Format !d,y d,y a,y !a,y !al,y !EXT,y EXT,y >d,x >a,x >al,x al,x >EXT,x d a al (EXT) (d) (!d) (a) (!a) (!al) EXT (d) ( www..com Program Counter Relative and Program Counter Relative Long Absolute Indirect Absolute Absolute Long Direct Indirect Direct Indirect Long Absolute Indexed Direct Page Accumulator Implied Addressing Direct Indirect Indexed Direct Indirect Indexed Long Direct Indexed Indirect Direct Indexed by X Stack Addressing Stack Relative Indirect Indexed Block Move Direct Indexed by Y Absolute Indexed by X Note: The alternate ! (exclamation point) is used in place of the | (vertical bar). The Western Design Center W65C816S 54 The Western Design Center, Inc. W65C816S Data Sheet 7.3.3.3 Note that the operand does not determine whether or not immediate address loads one or two bytes, this is determined by the setting of the status register. This forces the requirement for a directive or directives that tell the assembler to generate one or two bytes of space for immediate loads. The directives provided shall allow separate settings for the accumulator and index registers. 7.3.3.4 The assembler shall use the <, >, and ^ characters after the # character in immediate address to specify which byte or bytes will be selected from the value of the operand. Any calculations in the operand must be performed before the byte selection takes place. Table 7-3 defines the action taken by each operand by showing the effect of the operator on an address. The column that shows a two byte immediate value show the bytes in the order in which they appear in memory. The coding of the operand is for an assembler which uses 32-bit address calculations, showing the way that the address should be reduced to a 24-bit value. www..com Table 7-3 Byte Selection Operator Operand #$01020304 #<$01020304 #>$01020304 #^$01020304 One Byte Result 04 04 03 02 Two Byte Result 04 03 04 03 02 03 02 01 7.3.3.5 In any location in an operand where an address, or expression resulting in an address, can be coded, the assembler shall recognize the prefix characters <, |, and >, which force one byte (direct page), two byte (absolute) or three byte (long absolute) addressing. In cases where the addressing modes is not forced, the assembler shall assume that the address is two bytes unless the assembler is able to determine the type of addressing required by context, in which case that addressing mode will be used. Addresses shall be truncated without error in an addressing mode is forced which does not require the entire value of the address. For example, LDA $0203 and LDA |$010203 are completely equivalent. If the addressing mode is not forced, and the type of addressing cannot be determined from context, the assembler shall assume that a two byte address is to be used. If an instruction does not have a short addressing mode (as in LDA< which has no direct page indexed by Y) and a short address is used in the operand, the assembler shall automatically extend the address by padding the most significant bytes with zeroes in order to extend the address to the length needed. As with immediate address, any expression evaluation shall take place before the address is selected; thus, the address selection character is only used once, before the address of expression. 7.3.3.6 The (!) exclamation point character should be supported as an alternative to the | (vertical bar). 7.3.3.7 A long indirect address is indicated in the operand field of an instruction field of an instruction by surrounding the direct page address where the indirect address is found by square brackets; direct page addresses which contain sixteen-bit addresses are indicated by being surrounded by parentheses. 7.3.4 Comment Field The comment field may start no sooner than one space after the operation code field or operand field depending on instruction type. The Western Design Center W65C816S 55 The Western Design Center, Inc. W65C816S Data Sheet 8 Caveats Table 8-1 Caveats Compatibility Issue S (Stack) NMOS 6502 Always Page 1, 8 bits Always Page 0 Always less than 256 ie 8 Bits Always Page 0 Always less than 256 ie 8 Bits 8 bits N, V and Z flags invalid in decimal mode. D=unknown after reset. D not modified after interrupt W65C02 Always Page 1, 8 bits Always Page 0 Always less than 256 ie 8 Bits Always Page 0 Always less than 256 ie 8 Bits 8 bits N,V and Z flags valid in decimal mode. D=0 after reset/interrupt W65C02S Always page 1, 8 bits Always Page 0 Always less than 256 ie 8 Bits Always Page 0 Always less than 256 ie 8 Bits 8 bits N,V and Z flags valid in decimal mode. D=0 after reset /interrupt X (X Index Reg) www..com Y (Y Index Reg) A (Accumulator) W65C816S Always page 1 8 bits when(E=1), 16 bits when E=0 Indexed page zero always in page 0 (E=1), Cross page (E=0) Indexed page zero always in page 0 (E=1), Cross page (E=0) 8 bits (M=1), 16 bits (M=0) N,V and Z flags valid in decimal mode. D=0 after reset/interrupt (Flag Reg) Timing A.ABS,X,ASL,LSR, ROL with no Page Crossing B. Jump Indirect Operand =XXFF C. Branch Across Page D. Decimal Mode 7 cycles 5 cycles and invalid page crossing 4 cycles No add. cycles 6 cycles 6 cycles 4 cycles Add 1 cycle 6 cycles 6 cycles 4 cycles Add 1 Cycle 7 cycles 5 cycles 4 cycles No add. cycles 00FFFE,F(E=1) BRK bit=0 on stack if IRQ- NMIB, ABORTB 000FFE6,7 (E=0), X=X on stack always PBR not pushed (E=1) RTI, PBR, not pulled (E-1) PRB pushed (E=0) RTI, PBR pulled (E=0) BRK Vector FFFE,F BRK bit=0 on stack if IRQ, NMI FFFE,F BRK bit=0 on stack if IRQ, NMI FFFE,F BRK bit=0 on stack if IRQ, NMI Interrupt or Break Bank Address Memory Lock (ML) Indexed Across Page Boundary (d),y a,x a,y RDY Pulled during Write Cycle Not available Not available MLB=0 during Modify and Write cycles Extra read of last instruction fetch Processor stops Not available MB=0 during Modify and Write cycles Extra read of last instruction fetch Processor stops Not available Extra read of invalid address Ignored MLB=0 during Read Modify and Write cycles Extra read of invalid address Processor Stops The Western Design Center W65C816S 56 The Western Design Center, Inc. W65C816S Data Sheet 8.1 Stack Addressing When in the Native mode, the Stack may use memory locations 000000 to 00FFFFF. The effective address of Stack, Stack Relative, and Stack Relative Indirect Indexed addressing modes will always be within this range. In the Emulation mode, the Stack address range is 000100 to 0001FF. The following OpCodes and addressing modes will increment or decrement beyond this range when accessing two or three bytes: JSL, JSR (a,x), PEA, PEI, PER, PHD, PLD, RTL 8.2 www..com Direct Addressing 8.2.1 The Direct Addressing modes are often used to access memory registers and pointers. The effective address generated by Direct; Direct,X and Direct,Y addressing modes will always be in the Native mode range 000000 to 00FFFF. When in the Emulation mode, the direct addressing range is 000000 to 0000FF, except for [Direct] and [Direct],Y addressing modes and the PEI instruction which will increment from 0000FE or 0000FF into the Stack area. 8.2.2 When in the Emulation mode and DH is not equal to zero, the direct addressing range is 00DH00 to 00DHFF, except for [Direct] and [Direct],Y addressing modes and the PEI instruction which will increment from 00DHFE or 00DHFF into the next higher page. 8.2.3 When in the Emulation mode and DL in not equal to zero, the direct addressing range is 000000 to 00FFFF. 8.3 Absolute Indexed Addressing The Absolute Indexed addressing modes are used to address data outside the direct addressing range. The W65C02S addressing range is 0000 to FFFF. Indexing from page FFXX may result in a 00YY data fetch when using the W65C02S. In contrast, indexing from page ZZFFXX may result i ZZ+1,00YY when using the n W65C816S. 8.4 ABORTB Input 8.4.1 ABORTB should be held low for a period not to exceed one cycle. Also, if ABORTB is held low during the Abort Interrupt sequence, the Abort Interrupt will be aborted. It is not recommended to abort the Abort Interrupt. The ABORTB internal latch is cleared during the second cycle of the Abort Interrupt. Asserting the ABORTB input after the following instruction cycles will cause registers to be modified: 8.4.1.1 Read-Modify-Write: Processor sta tus modified if ABORTB is asserted after a modify cycle. 8.4.1.2 RTI: Processor status modified if ABORTB is asserted after cycle 3. 8.4.1.3 IRQB, NMIB, ABORTB BRK, COP: When ABORTB is asserted after cycle 2, PBR and DBR will become 00 (Emulation mode) or PBR will become 00 (Native mode). 8.4.2 The ABORT Interrupt has been designed for virtual memory systems. For this reason, asynchronous ABORTB's may cause undesirable results due to the above conditions 8.5 VDA and VPA Valid Memory Address Output Signals When VDA or VPA are high and during all write cycles, the Address Bus is always valid. VDA and VPA should be used to qualify all memory cycles. Note that when VDA and VPA are both low, invalid addresses may be generated. The Page and Bank addresses could also be invalid. This will be due to low byte addition only. The cycle when only low byte addition occurs is an optional cycle for instructions which read memory when the Index Register consists of 8 bits. This optional cycle becomes a standard cyc le for the Store instruction, all instructions using the 16-bit Index Register mode, and the Read-Modify-Write instruction when using 8- or 16-bit Index Register modes. The Western Design Center W65C816S 57 The Western Design Center, Inc. W65C816S Data Sheet 8.6 DB/BA operation when RDY is Pulled Low When RDY is low, the Data Bus is held in the data transfer state (i.e. PHI2 high). The Bank address external transparent latch should be latched on the rising edge of the PHI2 clock. 8.7 MX Output The MX output reflects the value of the M and X bits of the processor Status Register. The REP, SEP and PLP instructions may change the state of the M and X bits. Note that the MX output is invalid during the instruction cycle following REP, SEP and PLP instruction execution. This cycle is used as the OpCode fetch cycle of the www..com next instruction. 8.8 All OpCode s Function in All Modes of Operation 8.7.1 It should be noted that all OpCodes function in all modes of operation. However, some instructions and addressing modes are intended for W65C816S 24-bit addressing, and are therefore less useful for the emulation mode. The JSL, RTL, JMP al and JML instructions and addressing modes are primarily intended for W65C816S native mode use. 8.7.2 The following instructions may be used with the emulation mode even though a Bank Address is not multiplexed on the Data Bus: PHK, PHB and PLB 8.7.3 The following instructions have "limited" use in the Emulation mode: 8.7.3.1 The REP and SEP instructions cannot modify the M and X bits when in the Emulation mode. In this mode the M and X bits will always be high (logic 1). 8.7.3.2 When in the Emulation mode, the MVP and MVN instructions use the X and Y Index Registers for the memory address. Also, the MVP and MVN instructions can only move data within the memory range 0000 (Source Bank) to 00FF (Destination Bank) for the W65C816S, and 0000 to 00FF for the emulation mode. 8.9 Indirect Jumps The JMP (a) and JML (a) instructions use the direct Bank for indirect addressing, while JMP (a,x) and JSR (a,x) use the Program Bank for indirect address tables. 8.10 Switching Modes When switching from the Native mode to the Emulation mode, the X and M bits of the Status Register are set high (logic 1), the high byte of the Stack is set to 01, and the high bytes of the X and Y Index Registers are set to 00. To save previous values, these bytes must always be stored before changing modes. Note that the low byte of the S, X and Y Registers and the low and high byte of the Accumulator (A and B) are not affected by a mode change. 8.11 How Interrupts Affect the Program Bank and the Data Bank Registers 8.11.1 When in the Native mode, the Program Bank register (PBR) is cleared to 00 when a hardware interrupt, BRK or COP is executed. In the Native mode, previous PBR contents are automatically saved on Stack. 8.11.2 In the Emulation mode, the PBR and DBR registers are cleared to 00 when a hardware interrupt, BRK or COP is executed. In this case, previous contents of the PBR are not automatically saved. 8.11.3 Note that a Return from Interrupt (RTI) should always be executed from the same "mode" which originally generated the interrupt. The Western Design Center W65C816S 58 The Western Design Center, Inc. W65C816S Data Sheet 8.12 Binary Mode The Binary Mode is set whenever a hardware or software interrupt is executed. The D flag within the Status Register is cleared to zero. 8.13 WAI Instruction The WAI instruction pulls RDY low and places the processor in the WAI "low power" mode. NMIB, IRQB or RESB will terminate the WAI condition and transfer control to the interrupt handler routine. Note that an www..com ABORTB input will abort the WAI instruction, but will not restart the processor. When the Status Register I flag is set (IRQB disabled) the IRQB interrupt will cause the next instruction (following the WAI instruction) to be executed without going to the IRQB interrupt handler. This method results in the highest speed response to an IRQB input. When an interrupt is received after an ABORTB which occurs during the WAI instruction, the processor will return to the WAI instruction. Other than RESB (highest priority), ABORTB is the next highest priority, followed by NMIB or IRQB interrupts. 8.14 The STP Instruction The STP instruction disables the PHI2 clock to all internal circuitry. When disabled, the PHI2 clock is held in the high state. In this case, the Data Bus will remain in the data transfer state and the Bank address will not be multiplexed onto the Data Bus. Upon executing the STP instruction, the RESB signal is the only input which can restart the processor. The processor is restarted by enabling the PHI2 clock, which occurs on the falling edge of the RESB input. Note that the external oscillator must be stable and operating properly before RESB goes high. 8.15 COP Signatures Signatures 00-7F may be user defined, while signatures 80-FF are reserved for instructions on future microprocessors. Contact WDC for software emulation of future microprocessor hardware functions. 8.16 WDM OpCode Use The WDM OpCode may be used on future microprocessors. It performs no operation. WDM are the initials of William D. Mensch, Jr., the founder of WDC. 8.17 RDY Pulled During Write The NMOS 6502 does not stop during a write operation. In contrast, both the W65C02S and the W65C816S do stop during write operations 8.18 MVN and MVP Affects on the Data Bank Register The MVN and MVP instructions change the Data Bank Register to the value of the second byte of the instruction (destination bank address). The Western Design Center W65C816S 59 The Western Design Center, Inc. W65C816S Data Sheet 8.19 Interrupt Priorities The following interrupt priorities will be in effect should more than one interrupt occur at the same time: Highest Priority Lowest Priority RESB ABORTB, NMIB, IRQB 8.20 Transfers from 8-Bit to 16-Bit, or 16-Bit to 8-Bit Registers All transfers from one register to another will result in a full 16-bit output from the source register. The destination register size will determine the number of bits actually stored in the destination register and the www..com values stored in the processor Status Register. The following are always 16-bit transfers, regardless of the accumulator size: TCS, TSC, TCD and TDC Note: PHP and PLP are always 8 bit operations. 8.21 Stack Transfers When in the Emulation mode, a 01 is forced into SH. In this case, the B Accumulator will not be loaded into SH during a TCS instruction. When in the Native mode, the B Accumulator is transferred to SH. Note that in both the Emulation and Native modes, the full 16 bits of the Stack Register are transferred to the A, B and C Accumulators, regardless of the state of the M bit in the Status Register. 8.22 BRK Instruction The BRK instruction for the NMOS 6502, 65C02 and 65C816 is actually a 2 byte instruction. The NMOS device simply skips the second byte (i.e. doesn't care about the second byte) by incrementing the program counter twice. The 65C02 and 65C816 does the same thing except the assembler is looking for the second byte as a "signature byte". With either device (NMOS or CMOS), the second byte is not used. It is important to realize that if a return from interrupt is used it will return to the location after the second or signature byte. 8.23 Accumulator switching from 8 bit to 16 bit Care must be taken when switching from 16 bit mode to 8 bit mode then to 16 bit mode. The B register is restored so that the following code shows a potential problem: LONGA REP LDA STA LONGA SEP LDA STA LONGA REP STA ON #$20 #$2345 MIKE PFF #$20 #$01 SAM ON #$20 BOB Here BOB = $2301 and NOT $000V The Western Design Center W65C816S 60 The Western Design Center, Inc. W65C816S Data Sheet 9 9.1 * * www..com HARD CORE MODEL W65C816 Core Information The W65C816S core uses the same instruction set as the W65C816S The only functional difference between the W65C816S and W65C816S core is the RDY pin. The W65C816S RDY pin is bi-directional utilizing an active pullup. The W65C816S core RDY function is split into 2 pins, RDYIN and WAITN. The WAITN output goes low when a WAI instruction is executed. The W65C816S core will be a smaller die since the I/O buffers have been The outputs are the N-channel and P-channel output transistors drivers. The following inputs, if not used, must be held in the high state: RDY input, and ABORTB. IRQB, MIB, BE removed. * * * The timing of the W65C816S core is the same as the W65C816S. * 10 SOFT CORE RTL MODEL 10.1 W65C816 Synthesizable RTL-Code in Verilog HDL The RTL-Code (Register Transfer Level) in Verilog is a synthesizable model. The behavior of this model is equivalent to the original W65C816S hard core. The W65C816S RTL-Code is available as the core model and the W65C816S standard chip model. The standard chip model includes the soft core and the buffer ring in RTL-Code. Synthesizable cores are useful in ASIC design. The Western Design Center W65C816S 61 The Western Design Center, Inc. W65C816S Data Sheet 11 ORDERING INFORMATION W65C816S6PL-14 Description W65C = standard product Product Identification Number Foundry Process Blank = 1.2u 8 = .8u 6 = .6u Package P = Plastic Dual-In-Line, 40 pins PL = Plastic Leaded Chip Carrier, 44 pins Q = Quad Flat Pack, 44 pins Temperature/Processing DIP = 0C to + 70C PLCC and QFP = -40C to + 85C Speed Designator -14 = 14MHz W65C 816S 6 www..com PL -14 ___________________________________________________________________________ To receive general sales or technical support on standard product or information about our module library licenses, contact us at: The Western Design Center, Inc. 2166 East Brown Road Mesa, Arizona 85213 USA Phone: 480-962-4545 Fax: 480-835-6442 information@westerndesigncenter.com www.westerndesigncenter.com ______________________________________________________________________________ WARNING: MOS CIRCUITS ARE SUBJECT TO DAMAGE FROM STATIC DISCHARGE Internal static discharge circuits are provided to minimize part damage due to environmental static electrical charge build-ups. Industry established recommendations for handling MOS circuits include: 1. 2. 3. Ship and store product in conductive shipping tubes or conductive foam plastic. Never ship or store product in non-conductive plastic containers or non-conductive plastic foam material. Handle MOS parts only at conductive work stations. Ground all assembly and repair tools. The Western Design Center W65C816S 62 |
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